University of Alberta CMPUT329

CMPUT 329
COMPUTER ORGANIZATION AND ARCHITECTURE II

Department of Computing Science
University of Alberta

Fall 2003

Revised November 28, 2003

LATEST ANNOUNCEMENT:

Monday Dec. 01: Quiz #7 and Teaching Evaluation
Wednesday Dec. 03: Class Cancelled.
Final Exam: You will be allowed to bring one piece of paper with anything that you want written on it. The rule is that this piece of paper have to be written by hand and by you, without any mechanical or computer assistance. It cannot be a reproduction.
Past Midterms and Finals are linked to the page.

LECTURE TIME: MWF 11:00 11:50
LECTURE PLACE: Civil/Electrical Building (CEB) 231

INSTRUCTOR: José Nelson Amaral
                           Office: ATH 3-42
                           Office Hours: Wednesday, 10-11
                                                   Wednesday, 1-2

TEACHING ASSISTANT: Ashikur Rahman (Sections D01 (Tue) and D03 (Thur))
Chris Parker (Section D02 - Wed. morning)

Mailing List:

If you are registered for the Fall of 2003, you should have received emails on your ugrad.cs.ualberta.ca address. If you prefer to use a different address, or if you have not received any message, you should subscribe to the class mailing list by sending an email to:

Majordomo@cs.ualberta.ca

with no subject and the following line

subscribe cmput329
Some announcements will be made only through the class mailing list.

XUP Program Registration to the Xilinx University Program

In order to receive a certificate at the end of the term from the Xilinx University Program, you must register at the XUP Registration Site before October 01 2003. Here is the information that you will need for your registration:

Professor First: Jose
Professor Last: Amaral
Title: Associate Professor
Department: Computing Science
Address: Dept. of Computing Science - Univ. of Alberta
City: Edmonton
Province: Alberta
Country: Canada
Phone: (780) 492-5411
Email: amaral@cs.ualberta.ca
Course: CMPUT329
Course Name: Computer Organization and Architecture II
Semester: Fall 2003

Reading Assignment Quizzes (from Wakerly textbook)

September 10 (Wednesday), Chapter 1
September 15 (Monday), Chapter 2
September 19 (Friday), Chapter 3

Quiz Content
Date

Points

Quiz1

Chapter 1

September 10

2

Quiz2

Chapter 2

September 15

2

Quiz3

Chapter 3

September 19

2

Quiz4

Homework1

September 29

2

Quiz5

Homework2

October 15

3

Quiz6

Homework3

November 12

2

Quiz7

Homework4

December 01

2

Assignments

Solutions for selected exercises in the textbook are available here.
Homework1 (hw1.ps) (hw1.pdf) In-Class Quiz: September 29
Homework2 In-Class Quiz: October 15
Homework3 In-Class Quiz: November 12
Homework4 (hw4.ps) (hw4.pdf) In-Class Quiz: December 01

Labs

Laboratory Exercise Sug. Completion Date
Deadline

Points

Lab1

October 01

October 24

3

Lab2

October 09

October 24

4

Lab3

October 20

October 24

5

Lab4

November 12

December 05

6

Lab7

December 01

December 05

7

Detailed Submission Instructions are now available.
Pre-Lab Assignments are due at the beginning of the first lab section of the week in which the lab assignment work starts.
You have to demonstrate your lab in the lab section to your TA. Keep in mind that on the week of October 20-24 the TAs are likely to be very busy, you should demonstrate your working lab before the suggested completion date.
You should turn in your lab reports to your TA in your lab section as you complete them. October 24 at 11:00 in class is the last minute drop-dead deadline for you to turn in the reports for Lab1, Lab2, and Lab3.
You are invited to do Lab5 for an additional 4 points in your final grade. You will receive the 4 points if you complete the lab successfully and both submit a lab report and do a correct demonstration. You will receive partial credit if you demonstrated progress on Lab5, but do not complete it.

This is the lab web page.

Lectures

Topic0: Introduction (HTML) (Powerpoint))
Topic1: Boolean Logic (HTML) (Powerpoint)
Topic2: DeMorgan Laws (HTML) (Powerpoint))
Topic3: VHDL (HTML) (Powerpoint))
Topic4: Karnaugh Maps (HTML) (Powerpoint)
Topic5: Quine-McCluskey Algorithm (HTML) (Powerpoint)
Topic6: Testbenches (HTML) (Powerpoint)
Topic7: Timing Hazards (HTML) (Powerpoint)
Topic8: Documentation and Timing Diagrams (HTML) (Powerpoint)
Topic9: Three-State Buffers (HTML) (Powerpoint)
TopicA: Flip-Flops (HTML) ( Powerpoint)
TopicB: Sequential Circuits (HTML) (Powerpoint)
TopicC: State Minimization (HTML) (Powerpoint)
TopicD: State Assignment (HTML) (Powerpoint)
TopicE: Clock Skew and Clock Gating (HTML) (Powerpoint)
TopicF: Memories (HTML) (Powerpoint)
TopicG: FPGA Organization (HTML) (Powerpoint)
TopicH: Data Path (HTML) ( Powerpoint)
TopicI: Multi-Cycle Data Path (HTML) (Powerpoint)
TopicJ: Counters (HTML) (Powerpoint)
TopicK: Shift Registers (HTML) (Powerpoint)

Quizzes, Midterms and Finals

Year	Exam	Files	Solution
2003	Final	(.pdf) (.ps)
2003	Quiz #6	(.ps)	(.ps)
2003	Quiz #5	(.ps)	(.pdf) (.ps)
2003	Quiz #4	(.ps)
2003	Quiz #3	(.ps)	(.ps)
2003	Quiz #2	(.ps)	(.ps)
2003	Quiz #1	(.ps)	(.ps)
2003	Midterm	(.pdf) (.ps)
2002	Final	(.pdf) (.ps)
2002	Midterm	(.pdf) (.ps)
2001	Final	(.pdf) (.ps)
2001	Midterm	(.pdf) (.ps)
2000	Final	(.pdf) (.ps)
2000	Midterm	(.pdf) (.ps)

Calendar Description

*3 (fi 6) (either term, 3-0-3). Digital circuits, combinational systems, memory, register transfer, control logic design, CPU design, and advanced topics on micro-architectures.
Prerequisite: CMPUT 229. Credit may be obtained in only one of CMPUT 280, CMPUT 329 or EE 280.

Course Outline

Boolean Algebra

Algebraic Simplification

Applications of Boolean Algebra

Karnaugh Maps

Quine-McCluskey Method

Fundamentals of VHDL

Multi-Level Gate Networks

Multiplexes, Decoders, Read-Only Memories
Programmable Logic Arrays

Flip-Flops

Counters and Sequential Networks

Clocked Sequential Networks

Finite State Machines

The State Assignment Problem

Sequential Network Design

The Design of a Data Path

Memories

The Principle of Pipelining

Grades

Component	Date Due	Weight
Lab Assignments	TBA	25%
Midterm Exam	Oct. 20	25%
Quizzes	TBA	15%
Final Exam	Dec. 15, 9AM	35%

Textbook:

Wakerly, John F., Digital Design: Principles and Practices, Prentice Hall, Upper Saddle River, New Jersey, ISBN 0-13-089896-1.

VHDL Reference Books:

Yalamanchili, Introductory VHDL: From Simulation to Synthesis, 2001, Prentice Hall, Upper Saddle River, NJ, ISBN 0-13-080982-9.
Ashenden, Peter J., The Designer's Guide to VHDL, Morgan Kaufmann Pub., San Francisco, CA, ISBN 1-55860-674-2.

Contact Information:

Instructor's e-mail: amaral@cs.ualberta.ca
Teaching assistant's e-mail: TBA

University of Alberta
Computing Science

Quiz	Content	Date	Points
Quiz1	Chapter 1	September 10	2
Quiz2	Chapter 2	September 15	2
Quiz3	Chapter 3	September 19	2
Quiz4	Homework1	September 29	2
Quiz5	Homework2	October 15	3
Quiz6	Homework3	November 12	2
Quiz7	Homework4	December 01	2

Laboratory Exercise	Sug. Completion Date	Deadline	Points
Lab1	October 01	October 24	3
Lab2	October 09	October 24	4
Lab3	October 20	October 24	5
Lab4	November 12	December 05	6
Lab7	December 01	December 05	7