Click here to start

Table of contents

CMPUT329 - Fall 2003

Reading Assignment

PowerPoint Presentation

Slide 4

EPROMs (Erasable Programmable Read Only Memories)

Address Decoding on a Microprocessor System

The 74x139 Decoder

Slide 8

Slide 9

Slide 10

Slide 11

Slide 12

Slide 13

Slide 14

Slide 15

Address Decoding

Slide 17

Slide 18

Slide 19

Slide 20

Slide 21

Slide 22

Slide 23

Slide 24

Types of Memories

Random Access Memories (RAMs)

Static-RAM Control Inputs

A 2nï‚´b SRAM

SRAMs (Static Random Access Memories)

Accesses to SRAM

Slide 31

Slide 32

Slide 33

Slide 34

SRAM with Bi-directional Data Bus

Internal Address Decoding

Slide 37

Static-RAM Read Timing

Slide 39

Static-RAM Write Timing

Dynamic Memory Cell

Writing 1 in a Dynamic Memories

Writing 0 in a Dynamic Memories

Destructive Reads

Recovering from Destructive Reads

Forgetful Memories

Refreshing the Memory

Refreshing Frequency

Refreshing Memory

Internal Structure of a 64K ï‚´ 1 DRAM

Slide 51

Slide 52

Improved DRAMs

Fast Page Mode DRAMs

Slide 55

Enhanced Data Output RAMs (EDO-RAM)

Slide 57

Synchronous DRAMs (SDRAM)

SDRAM Burst Read Cycle


The Rambus DRAM (RDRAM)

SDRAM Memory Systems

RDRAM Memory Systems

Internal RDRAM Organization

SDRAM Protocol

RDRAM Protocol

Bank Conflicts

SDRAM Bank Conflicts

RDRAM Banks ï‚´ SDRAM Banks

Dual In-line Memory Module (DIMM)

Rambus In-line Memory Module (RIMM)

A picture of RIMMs

Further Reading

Author: Jose Nelson Amaral