VHDL FAQ

You may also want to consult the Errors list.
 

Q: Are there any online VHDL tutorials?

A1: Green Mountain Computing has a tutorial, or (same, different format)

A2: Check out the language assistant in the HDL editor for help with syntax and component code templates (in Tools menu of HDL editor, or first button after the dropbox in the middle of the toolbar.)
 

Q: Why did "operation fail" when I tried to create my component?

A: Maybe not enough memory. Foundation uses lots of RAM, and also it has a memory leak, so after a while you may not have enough RAM to work properly. Check the messages on the main screen for "could not allocate memory" error messages (red) (they don't use a popup to tell you, it just kinda happens...)
 

Q: Is there a way to check the syntax of my VHDL without having to synthesize the design?

A: use "Synthesis -> Check Syntax". (Also, second button on toolbar after dropbox ).
 

Q: Why isn't my VHDL component listed in the project?

A:  You need to add the file to the project (Project -> Add Files)
 

Q: Why does my VHDL not synthesize?

A:

You may also want to check the Errors list or the Xilinx answers database (paste in your error).
 

Q: How can I copy my error message from the HDL editor?

A: Synthesis -> View Report will open a new text editor window where you can copy your error or warning messages.

Q: How do I convert from integers to std_logic_vectors or vice-versa?

A:  First of all, you must include the library that contains these conversion functions: 'use ieee.numeric_std.all;'.  Because VHDL is a strongly-typed language, this kind of conversion requires an intermediary type called unsigned.  To got from an integer to a std_logic_vector you should use:

my_slv <= std_logic_vector(to_unsigned(my_integer));

      For the conversion the other way, you should use:
my_integer <= to_integer(unsigned(my_slv));

Q:  What is clock-edge specification and when and how do I use it?

A:  Very often in VHDL you want to synchronize an action based on when an event occurred.  For example, if you want to check the state of a signal every so often, you would use a clock signal (like the clock in the board) and check the signal every time the clock signal turned from 0 to 1.  This change from 0 to 1 is called the rising edge of the clock and programming a behaviour to occur on this edge is clock-edge specification.  You can use this for any signal, not just a clock signal, as long as you want to synchronize something (for example, we use it during the labs that require a keyboard input by using the keyboard press signal as the clock.)  You can use this method of specification in the following way:
process(clk, rst)
begin
    if rst = '1' then
       -- set initial signal values
    elsif clk'event and clk = '1' then   -- the clock signal changed to 1
       -- what to do on the rising edge
    end if;
end process

There are a few restrictions to this, however.  One is that once you have this set-up, you cannot specify any other clock edges in this process (for example, if you had a second clock, you could not use it in the same way as the first one in the same process).  Also, you cannot specify the rising edge and the falling edge of the same clock in the same process.  The other restriction is that any signal you assign a value to in this framework cannot have a value specified in any other part of the code.  That is, once you have a signal assigned based on a clock-edge, you cannot assign it in a non-clock setting.

Q: What is Structural VHDL and how do I use it?

A:    Structural VHDL is a form of the language in which one VHDL module is built using other modules within it.  Suppose for example that you have built three modules that you use in concert quite frequently.  Rather than having to connect them separately every time that you need them, you would use structural VHDL to combine them into one module.  Also, when you want to implement a project made up of several components, you need a top-level component describing how they are connected.  This top-level file will have to be written as structural VHDL.  Here is a brief example.


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Created by Paul Berube, 2001, Paras Mehta, 2003.