Error: In translate phase: net has illegal connection etc, but I checked and everything is OK.
-- Try deleting the net, pads, bufs that are mentioned in the error
and re-doing them. This will help make sure that you did not miss
something, and also can correct errors that exist "behind the scenes"
(program glitches) that you cannot find or fix otherwise.
Error: The net '/component/net_name' has more than one driver. (FPGA-CHECK-5)
-- You can't do signal assignment to the same signal from more than
ONE process. Try using internal signals in each process and using
combinatorial logic to produce the output value, or move all the code
for that signal into the same process. Also, you may want to break the
component into two halves that "talk" to each other (one part for each
process etc...).
Error: Enabling expression not permitted outside wait statements on line 27 (VHDL-2251)
-- You can't put other conditions in the same 'if' clause as clk edge selection. eg: You can't do:
if rst = '1' and clk'event and clk = '1' then ...
You need to do this as:
if clk'event and clk = '1' then if rst = '1' then ...
Error: All possible string values of selector type not covered by choices. (VSS-1032)
-- If you use a case statement, you can't leave any value unspecified - you need to enumerate all the possible values for the element you are switching over. However, even if you list all the values, it might still complain. In this case, just add a
when others = > <whatever you want - I recommend assignment to "don't care" (eg: sig < = '-') or null clause>
to the end.
Error: Cannot update ports of mode IN or LINKAGE. (VSS-798) (FPGA-hci-hdlc-unknown)
-- You are using an input on the left side of a signal assignment!
(ie you are trying to assign to an input - you can only assign to
outputs!!
Error: Clock variable 'clk' is being used as data . (HDL-175)
-- clk is used in a process with edge specification, but you are
also using it in a signal assignment (on right hand side). Check that
clk is the variable you want in both places. Probably, the clk in the
process is supposed to be clkin, or the clk in the assignment is
supposed to be tmpclk (perhaps different names, but you get the
idea...).
Error: Can not determine type of right hand side. The following interpretations were considered for the right hand side: (none). (VSS-1049) (FPGA-hci-hdlc-unknown)
-- The left and right side of a signal assignment are not of the same type. Eg: assigning a STD_LOGIC_VECTOR to a signal of type STD_LOGIC.
Error: Tried to use a synchronized value in routine NAME
-- You can't specify more than one clock edge in a single process. For example, this means that you cannot use both the rising and falling edge of a clock in the same process, and you cannot have edge-triggered actions for more than one signal (ie only one clock).
Error:
Could not find NET 'NAME' in design 'NAME'
--There could be two causes for this. First of all, the net specified in not in your design but is in your constraints file. In this case, you can either add the net or comment it out of the constraints file. The other, harder to find problem is that the net has been optimized out of your design. This will happen if you have an input but it isn't used anywhere in your design. You could scroll up to the synthesis messages and see if there is a warning such as "Port 'NAME' has no net attached to it - no pad cells inserted at this port." If this is the case, you must either use the net in your design or comment it out of your constraints file in order to implement your design.