architecture entity_arch of new_entity is
-- first you must declare your
components and signals:
component first_component is
port(
-- port declaration
just like in entity declaration
-- you could copy this from the file and
-- replace 'entity' with 'component'
input_port: in std_logic;
...
output_port: out std_logic
);
end component;
...
-- now you
have to declare the signals you need
signal signal_1, ..., signal_n : std_logic;
...
begin
-- components have to be instantiated
now:
first_1 : first_component
port map
( -- you can connect signals
explicitly
input_port => signal_1;
...
output_port => signal_2;
);
-- you can have multiple instances
of one component
first_2 : first_component
-- you can
also connect signals implicitly based on
-- order listed
port map
(signal_2, ..., signal_3);
-- because
signal_2 is the output of one component and
-- the input of another, it means that this pair of
-- outputs and inputs are connected
... more
instantiations or other code
-- you can also map the ports of your
current entity
-- to the components in your design
-- Note: This file has all the
same capabilities of other
-- VHDL files. That is, you can have processes, functions
-- and use this entity in other higher level files.
-- That being said, it is recommended that your structural
-- description contain only component instantiations and
-- not behavioural code
end architecture;