Three-State Drivers in VHDL (cont.)

process (G_L, SEL, B)

begin

if G_L=‘0’ and SEL = “01” then X <= To_StdULogicVector(B);

else X <= (others => ‘Z’);

end if;

end process;

process (G_L, SEL, C)

begin

if G_L=‘0’ and SEL = “10” then X <= To_StdULogicVector(C);

else X <= (others => ‘Z’);

end if;

end process;

process (G_L, SEL, D)

begin

if G_L=‘0’ and SEL = “11” then X <= To_StdULogicVector(D);

else X <= (others => ‘Z’);

end if;

end process;

end V3states;

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