Three-State Drivers in VHDL

library IEEE;

use IEEE.std_logic_1164.all;

entity V3statex is

port (

G_L: in STD_LOGIC; -- Global output enable

SEL: in STD_LOGIC_VECTOR (1 downto 0); -- Input select 0, 1, 2, 3 ==> A, B, C, D

A, B, C, D: in STD_LOGIC_VECTOR (1 to 8); -- Input buses

X: out STD_ULOGIC_VECTOR (1 to 8) -- Output bus (three-state)

);

architecture V3states of V3statex is

begin

process (G_L, SEL, A)

begin

if G_L=‘0’ and SEL = “00” then X <= To_StdULogicVector(A);

else X <= (others => ‘Z’);

end if;

end process;

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