PPT Slide
inputA
inputB
output
result
result
operation
operandA
operandB
Logic Module
Arithmetic Module
operation
operandA
operandB
MUX
component mux
port(
selection: in std_logic;
inputA: in std_logic_vector (7 downto 0);
inputB: in std_logic_vector (7 downto 0);
output: out std_logic_vector (7 downto 0);
);
end component;
selection
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