On Tue, 30 Oct 2001, Neil S. Verkland (ROCKDOG) wrote:
>
> I'm going through some old slides trying to do my due-diligence so I can
> improve on the final. I have a question about slide 25/35 on flip flops.
>
> The title is S-R latch using NAND gates.
> I wnt through the logic truth tabel for the second diagram assuming that
> the 2 gates were NAND gates (they look like NOR gates) and I got a
> different set of results:
>
> S R | Q QN
> --------------
> 0 0 1 1
> 0 1 1 0
> 1 0 0 1
> 1 1 LQ LQN
>
> Did I do it wrong (I used NAND gates) or is the slide showing NOR gates
> and is therefor titled wrong?
>
Good question Neil.
The top one uses NAND gates. The representation is making use of
the following DeMorgan law:
(A.B)' = A' + B'
Thus those gates that look like an ON with inversions at the inputs
are actually NANDs.
The bottom S-R uses NOR gates. Notice the difference in the logic
levels of S and R (active low for the top latch and active high
for the bottom ones).
Cheers,
Nelson
/
\ / / Jose Nelson Amaral - amaral@cs.ualberta.ca
) / ( Associate Professor
/ / \ Dept. of Computing Science - University of Alberta
( / ) Edmonton, Alberta, Canada, T6G 2E8
\ O / Phone: (780)492-5411 Fax: (780)492-1071
\ / http://www.cs.ualberta.ca/~amaral
`----'
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