CMPUT 605-FPGA  ADVANCED TOPICS IN COMPILERS: EFFICIENT PROGRAMMING OF FIELD PROGRAMABLE GATE ARRAYS Department of Computing Science  University of Alberta

Winter 2017

TIME: TR 1400-1520
INSTRUCTORS: José Nelson Amaral, Karim Ali
 

Calendar Description:   Study the issues involved with the design and implementation of tools that support efficient programming of Field-Programmable Gate Arrays (FPGAs), including programming models, compilation solutions, specific code transformation techniques, architecture of existing platforms and the trading of functionality and maintenability for performance.

Course Description and Goals:

Extensive literature on the issue of supporting the programmability of FPGAs has focused on reconfigurability. Until recently reconfigurable computing was the main motivation to include an FPGA in a system design. However, recent concern for total energy consumption in large data centres have turned the attention of designers to the use of FPGAs to obtain higher performance at lower energy budget for important applications. A major commodity chip manufacturer, Intel, has acquired one of the major FPGA suppliers, Altera, and has proceed to integrate FPGAs into commodity off-the-shelf processors. Thus, for the first time there is the opportunity to explore FPGA solutions in large scale.

The main goal of this individual studies course will be to study both the academic literature and the open-source development community to establish the state of the art for supporting the programming of FPGAs and to identify opportunities for research in this area. The activities of the course will include discussion of published research papers in a seminar-style environment as well as the search, download, installation, and experimentation with existing open-source tools or tools offered by vendors with academic licenses. The students will also be tasked with creating implementation of solutions to sample problems in FPGAs and then to design strategies to improve such solutions.

Grading:

Class Presentations        30%
Homeworks                    20%
Practical Experiments    20%
Final Paper                      30%

Course Plan:

• January 06 - February 12: Literature Review:
  bi-weekly meetings for presentation/discussion of papers;
• February 13 - March 17: Exploration of existing tools and first programming assignment:
  students will explore existing tools for programming FPGAs and will execute at least one programming assignment using one or multiple tools so that they can understand the advantages and shortcomings of each tool.
• March 17 - April 15: Specification of Tool Improvements and Formulation of Research Problems:
  bi-weekly meetings to review tool designs, specify improvements and formulate potential research problems;

Literature:

• S. Hauck, A. Dehon, Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Morgan Kaufmann, 2008.
• Nitin Chugh, Vinay Vasista, Suresh Purini, and Uday Bondhugula. A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs. In Proceedings of the 2016 International Conference on Parallel Architectures and Compilation (PACT '16), pages 327-338. DOI: https://doi.org/10.1145/2967938.2967969
• Schuyler Eldridge, Amos Waterland, Margo Seltzer, Jonathan Appavoo, and Ajay Joshi. Towards General-Purpose Neural Network Computing. In Proceedings of the 2015 International Conference on Parallel Architecture and Compilation (PACT '15), pages 99-112. DOI: https://doi.org/10.1109/PACT.2015.21
• Davor Capalija and Tarex S. Abdelrahman. Towards Synthesis-Free JIT Compilation to Commodity FPGAs. In Field-Programmable Custo Computing Machines (FCCM) 2011. DOI: https://doi.org/10.1109/FCCM.2011.25
• Joshua Auerback, David F. Bacon, Ioana Burcea, Perry Cheng, Stephen J. Fink, Rodric Rabba and Sunil Shukla. A compiler and runtime for heterogeneous computing. In Design Automation Conference (DAC) 2012. DOI: https://doi.org/10.1145/2228360.2228411
• Fernando A. Escobar, Xin Chang and Carlos Valderrama. Suitability Analysis of FPGAs for Heterogeneous Platforms in HPC. In IEEE Transactions on Parallel and Distributed Systems (PDS) 2016. DOI: https://doi.org/10.1109/TPDS.2015.2407896
• Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz Czajkowski, Stephen D. Brown and Jason H. Anderson. LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems. In ACM Transactions on Embedded Computing Systems (TECS) 2013. DOI: https://doi.org/10.1145/2514740
• L. Semeria and G. De Micheli, "Resolution, optimization, and encoding of pointer variables for the behavioral synthesis from C," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 213-233, Feb 2001. DOI: 10.1109/43.908442
• S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov and E. M. Panainte, "The MOLEN polymorphic processor," in IEEE Transactions on Computers, vol. 53, no. 11, pp. 1363-1375, Nov. 2004. DOI: 10.1109/TC.2004.104
• Panainte, E. M., Bertels, K., & Vassiliadis, S. (2007). The molen compiler for reconfigurable processors. ACM Transactions on Embedded Computing Systems (TECS), 6(1), 6. DOI: http://dx.doi.org/10.1145/1210268.1210274

University of Alberta

Computing Science