CMPUT429/CMPE382 Winter 2001
Advantages of HW (Tomasulo) vs. SW (VLIW) Speculation
Data Flow
Data Dependency Graph (Data Flow Graph)
Instruction Sequences
Advantages of Dynamic Scheduling
HW Schemes: Instruction Parallelism
Dynamic Scheduling Step 1
A Dynamic Algorithm: Tomasulo’s Algorithm
Tomasulo Algorithm
Tomasulo Organization
Reservation Station Components for Scoreboard Scheme
Reservation Station Components for Tomasulo Algorithm
Three Stages of Tomasulo Algorithm
Tomasulo Example
Tomasulo Example Cycle 1
Tomasulo Example Cycle 2
Tomasulo Example Cycle 3
Tomasulo Example Cycle 4
Tomasulo Example Cycle 5
Tomasulo Example Cycle 6
Tomasulo Example Cycle 7
Tomasulo Example Cycle 8
Tomasulo Example Cycle 9
Tomasulo Example Cycle 10
Tomasulo Example Cycle 11
Tomasulo Example Cycle 12
Tomasulo Example Cycle 13
Tomasulo Example Cycle 14
Tomasulo Example Cycle 15
Tomasulo Example Cycle 16
(skipping many cycles)
Tomasulo Example Cycle 55
Tomasulo Example Cycle 56
Tomasulo Example Cycle 57
Tomasulo Drawbacks
Tomasulo Loop Example
Loop Example
Loop Example Cycle 1
Loop Example Cycle 2
Loop Example Cycle 3
Loop Example Cycle 4
Loop Example Cycle 5
Loop Example Cycle 6
Loop Example Cycle 7
Loop Example Cycle 8
Loop Example Cycle 9
Loop Example Cycle 10
Loop Example Cycle 11
Loop Example Cycle 12
Loop Example Cycle 13
Loop Example Cycle 14
Loop Example Cycle 15
Loop Example Cycle 16
Loop Example Cycle 17
Loop Example Cycle 18
Loop Example Cycle 19
Loop Example Cycle 20
Why can Tomasulo overlap iterations of loops?
Tomasulo’s scheme offers 2 major advantages
What about Precise Interrupts?
Relationship between precise interrupts and speculation:
HW support for precise interrupts
Four Steps of Speculative Tomasulo Algorithm
What are the hardware complexities with reorder buffer (ROB)?
Summary
Email: amaral@cs.ualberta.ca
Home Page: www.cs.ualberta.ca
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