CMPUT429/CMPE382 Winter 2001

3/7/02


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Table of Contents

CMPUT429/CMPE382 Winter 2001

Recall from Pipelining Review

Ideas to Reduce Stalls

Instruction-Level Parallelism (ILP)

Data Dependence and Hazards

Data Dependence and Hazards

Name Dependence #1: Anti-dependence

Name Dependence #2: Output dependence

ILP and Data Hazards

Control Dependencies

Control Dependence Ignored

Exception Behavior

Static Branch Prediction

Running Example

FP Loop: Where are the Hazards?

FP Loop Showing Stalls

Revised FP Loop Minimizing Stalls

Unroll Loop Four Times (straightforward way)

Unrolled Loop Detail

Unrolled Loop That Minimizes Stalls

Compiler Perspectives on Code Movement

Where are the name dependencies?

Where are the name dependencies?

Where are the name dependencies?

Compiler Perspectives on Code Movement

Steps Compiler Performs to Unroll

When a Loop is Parallel?

How to find dependences?

When a Loop is Parallel?

When a Loop is Parallel?

When a Loop is Parallel?

When a Loop is Parallel?

When a Loop is Parallel?

When a Loop is Parallel?

Loop Parallelization?

Hardware Support for Exposing More Parallelism at Compile-Time

Hardware Support for Exposing More Parallelism at Compile-Time

Exception Behavior Support

What if We Could Change the Instruction Set?

VLIW: Very Large Instruction Word

Example of a VLIW Architecture: IA-64. Suggested Reading

IA-64 Instruction Group

Instruction Bundles

Bundles

Templates

Control Dependency Preventing Code Motion

Control Speculation

Control Speculation

Ambiguous Memory Dependencies

Data Speculation

Moving Up Loads + Uses: Recovery Code

ld.c, chk.a and the ALAT

ld.c, chk.a and the ALAT

Not a Thing (NaT)

If-conversion

Trace Scheduling

Superscalar v. VLIW

Problems with First Generation VLIW

Intel/HP IA-64 “Explicitly Parallel Instruction Computer (EPIC)”

IA-64 Registers

IA-64 Registers

Intel/HP IA-64 “Explicitly Parallel Instruction Computer (EPIC)”

5 Types of Execution in Bundle

Itanium™ Processor Silicon (Copyright: Intel at Hotchips ’00)

Itanium™ Machine Characteristics (Copyright: Intel at Hotchips ’00)

PPT Slide

10 Stage In-Order Core Pipeline (Copyright: Intel at Hotchips ’00)

Itanium processor 10-stage pipeline

Itanium processor 10-stage pipeline

Comments on Itanium

Peformance of IA-64 Itanium (Source: Microprocessor Report Jan 2002)

Summary#1: Hardware versus Software Speculation Mechanisms

Summary#2: Hardware versus Software Speculation Mechanisms cont’d

Summary #3: Software Scheduling

Author: Randy H. Katz

Email: amaral@cs.ualberta.ca

Home Page: www.cs.ualberta.ca

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