CMPUT429/CMPE382 Winter 2001
Main Memory Background
Fast Memory Systems: DRAM specific
Main Memory Organizations
Main Memory Performance
Independent Memory Banks
Avoiding Bank Conflicts
Finding Bank Number and Address within a bank
Fast Bank Number
DRAMs per PC over Time
Main Memory Summary
Vitual Memory
Virtual to Physical Mapping
Virtual Memory (VM) Terminology
Address Translation
The for memory-hierarchy questions for Virtual Memory
Fast Address Translation
Protecting Processes (minimum protection system)
2. Fast hits by Avoiding Address Translation
2. Fast Cache Hits by Avoiding Translation: Index with Physical Portion of Address
3: Fast Hits by pipelining Cache Case Study: MIPS R4000
Case Study: MIPS R4000
R4000 Performance
What is the Impact of What You’ve Learned About Caches?
Alpha 21064
Alpha Memory Performance: Miss Rates of SPEC92
Alpha CPI Components
Pitfall: Predicting Cache Performance from Different Prog. (ISA, compiler, ...)
Cache Optimization Summary
Email: amaral@cs.ualberta.ca
Home Page: www.cs.ualberta.ca
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