CMPUT429 - Winter 2002

2/4/02


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Table of Contents

CMPUT429 - Winter 2002

Address Decoding

Address Decoding on a Microprocessor System

Types of Memories

Random Access Memories (RAMs)

Static-RAM Control Inputs

A 2n?b SRAM

SRAMs (Static Random Access Memories)

Accesses to SRAM

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SRAM with Bi-directional Data Bus

Internal Address Decoding

Static-RAM Read Timing

Static-RAM Read Timing

Static-RAM Write Timing

Dynamic Memory Cell

Writing 1 in a Dynamic Memories

Writing 0 in a Dynamic Memories

Destructive Reads

Recovering from Destructive Reads

Forgetful Memories

Refreshing the Memory

Internal Structure of a 64K ? 1 DRAM

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Improved DRAMs

Fast Page Mode DRAMs

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Enhanced Data Output RAMs (EDO-RAM)

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Synchronous DRAMs (SDRAM)

SDRAM Burst Read Cycle

DDR SDRAM

The Rambus DRAM (RDRAM)

SDRAM Memory Systems

RDRAM Memory Systems

Internal RDRAM Organization

RDRAM Banks ? SDRAM Banks

Further Reading

Author: Jose Nelson Amaral

Email: amaral@cs.ualberta.ca

Home Page: www.cs.ualberta.ca

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