Table of Contents
CMPUT429/CMPE382 Winter 2001
What is Pipelining?
Pipelining: Its Natural!
Sequential Laundry
Pipelined Laundry Start work ASAP
Pipelined Laundry Start work ASAP
PPT Slide
5 Steps of MIPS Datapath Figure 3.1, Page 130, CA:AQA 2e
5 Steps of MIPS Datapath Figure 3.4, Page 134 , CA:AQA 2e
Steps to Execute Each Instruction Type
Pipeline Stages
Pipeline Throughput and Latency
Pipeline Throughput and Latency
Pipeline Throughput and Latency
Pipeline Throughput and Latency
Pipeline Throughput and Latency
Pipeline Throughput and Latency
Pipeline Throughput and Latency
Pipeline Throughput and Latency
Pipeline Throughput and Latency
Pipeline Throughput and Latency
Pipelining Lessons
Computer Pipelines
Visualizing Pipelining Figure 3.3, Page 133 , CA:AQA 2e
Its Not That Easy for Computers
One Memory Port/Structural Hazards Figure 3.6, Page 142 , CA:AQA 2e
One Memory Port/Structural Hazards Figure 3.7, Page 143 , CA:AQA 2e
Data Hazard on R1 Figure 3.9, page 147 , CA:AQA 2e
Three Generic Data Hazards
Three Generic Data Hazards
Three Generic Data Hazards
Three Generic Data Hazards
Forwarding to Avoid Data Hazard
HW Change for Forwarding Figure 3.20, Page 161
Data Hazard Even with Forwarding Figure 3.12, Page 153
Data Hazard Even with Forwarding Figure 3.13, Page 154
Software Scheduling to Avoid Load Hazards
Why the fast code is faster?
Control Hazard on Branches Three Stage Stall
Example: Branch Stall Impact
Pipelined MIPS Datapath Figure 3.22, page 163, CA:AQA 2/e
Four Branch Hazard Alternatives
Four Branch Hazard Alternatives
Delayed Branch
Fig. 3.28
Delayed Branch
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Author: Jose Nelson Amaral
Email: amaral@cs.ualberta.ca
Home Page: www.cs.ualberta.ca
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