Three-State in VHDL and STD_ULOGIC
In VHDL, there is no explicit language construct for joining
three-state outputs into a bus.
If a signal is driven in two or more different processes, the VHDL
automatically joins them together. I.e., signals that appear on the
lefthand side of a signal statement in two or more processes
are joined together (as long as they have the appropriate type).
An unresolved type has an associated resolution function that
is called every time an assignment is made to a signal of that type.
When the signal has multiple drivers, the type resolution function
resolves the value of the signal.