Checking Output
Output read as a normal signal read
Checking done with assert-report-severity
verify: process(output)
begin
if clk'event and clk = '0' then
if (opcode = AND_OP)
assert (alu_result = operand1 and operand2)
report “Output is incorrect”
severity error;
end if;
end if;
end process;
Falling edge allows signal to be checked
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