Testbench Structure
architecture behaviour of testbench is
signal clk, rst : std_logic;
constant clk_period : time := 5 ns;
done <= true when condition else
clk <= '0' when rst = '1' else
not clk after clk_period when not done
Condition indicates simulation is over. e.g:
- time period has elapsed
- iterations completed
- end of input file reached
Basic signals are clock, reset, and termination:
- not active during reset
- oscillates until done
- brief pulse for reset of all signals in the design