M. Karnaugh, “The Map Method for Synthesis of
Combinatorial Logic Circuits”, Transactions of
the American Institute of Electrical Engineers,
Communications and Electronics, Vol. 72,
pp. 593-599, November 1953. and
A Karnaugh Map is a graphical tool to assist on the
minimization of logic equations.
Similar to a truth table, a Karnaugh Map specifies
a value for each combination of inputs.