On Tue, 16 Oct 2001, Bernard Ebinu wrote:
> Hi Dr. Amaral,
>
> I just have a quick question. Why is it impossible for you to attain a
> static-0 hazard in an AND-OR circuit?
>
To have a static-0 hazard, it must be possible for you to get a momentary
1 when you should actualy have only 0.
The hazard occurs when there is an interference between two transitions
that are incoming into the last gate of the circuit (as shown in
slide 7 of Topic6 --- in that case it is the timing between the top
input to the OR and the bottom input to the OR that causes the hard).
For the OR gate of a standard two-level AND-OR circuit to have an static-0
hazard, the output of the OR gate would have to be originally at 0 (which
means all inputs are 0). The only way for the glitch to occur would be for
there to be two transitions in the SAME input.
Notice that if a "1" glitch was produced somewhere earlier in the circuit,
the standard two-level AND-OR circuit may propagate the glitch, but it
will not generate one.
Cheers,
Nelson
/
\ / / Jose Nelson Amaral - amaral@cs.ualberta.ca
) / ( Associate Professor
/ / \ Dept. of Computing Science - University of Alberta
( / ) Edmonton, Alberta, Canada, T6G 2E8
\ O / Phone: (780)492-5411 Fax: (780)492-1071
\ / http://www.cs.ualberta.ca/~amaral
`----'
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