On Mon, 15 Oct 2001, Neil S. Verkland (ROCKDOG) wrote:
>
> In question 5.13 could you clarify this a bit?
>
> The IC is 74XL86. When the book says '86 3 level and '86 2 level
> does that mean that we can assume on one pass through the chip we can do a
> 3 level XOR operation (if we wanted) and on another pass we could do a 2
> level using the same chip? I kinda got that kind of feel from the lecture.
Neil:
I have no idea what the (2 levels) (3 levels) in the Table 5-2 is
suppose to mean. I got the data specs from Fairchild for the 74LS86
(if you search for "74LS86" on google you will find it), and could
not find anything about "levels" in this device. I also did not find
references in the text to these levels.
If anyone has a plausible explanation for what these levels are suppose
to mean, please email me.
As far as the homework, use the data from the (2 levels) line.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The objective of the homework is for you to make sure that you
understand this kind of analysis. Thus let us just make sure that
we all use the same data to make grading easier.
> I hope the answer to this will clarify the second part of the question
> also. I don't understand how we are to find a "single" worst-case delay
> when it is very clear that there is no possible way to finish a 4level
> logic gate will only one pass through a three level IC. Am I missing
> something?
A "single worst case delay" refers to tpHL an tpLH. Instead of using
different values for these transitions, you should use only one value
(the maximum obviously) and find out the worst case delay for the entire
circuit.
>
> ----
> Neil S. Verkland Email: neilv@ugrad.cs.ualberta.ca
> if ((j%6)!=54lopg2qw^^^^^^^^^^^^^^^^^^^^^^ "Kitty! Down from my keyboard, NOW!"
>
--Cheers,
Nelson
/ \ / / Jose Nelson Amaral - amaral@cs.ualberta.ca ) / ( Associate Professor / / \ Dept. of Computing Science - University of Alberta ( / ) Edmonton, Alberta, Canada, T6G 2E8 \ O / Phone: (780)492-5411 Fax: (780)492-1071 \ / http://www.cs.ualberta.ca/~amaral `----'
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