On Sat, 13 Oct 2001, Paul Berube wrote:
>
>
> a student sent Ashique and me this question, but since we don't have the
> text I'm not sure we can be of much help...
>
Please send homework related questions to me.
Lab related questions should be sent to all three of
us (Paul Berube <berube@ugrad.cs.ualberta.ca>, "A.K.M. Ashikur
Rahman" <ashikur@cs.ualberta.ca>, and myself).
> ---------- Forwarded message ----------
> Date: Fri, 12 Oct 2001 21:29:24 -0600 (MDT)
> From: Daniel Black <black@ugrad.cs.ualberta.ca>
> To: ashikur@cs.ualberta.ca
> Cc: berube@ugrad.cs.ualberta.ca
> Subject: hw 5.48
>
>
> Hey,
> I really don't understand what question 5.48 is saying. If
> the circuit can be drawn with a single 74x148, then are
> we just supposed to redraw the same 74x148 and rename some
> of the variables to the ones that are given to us? Or do we keep
> the gate structure and redraw the internal wiring around those
> gates?
>
Daniel:
The point of the exercise is to verify if you understand
active-high, active-low logic well.
Just draw the block representing the 74x148 as shown on page
378, and name the signals that are connected to it in order
to obtain the specification given in the question. The trick
is to obtain active-high outputs with reverse priority order
(then the standard 74x148, without using extra gates). Study
carefully the truth table on page 378 to figure it out.
Cheers,
Nelson
/
\ / / Jose Nelson Amaral - amaral@cs.ualberta.ca
) / ( Associate Professor
/ / \ Dept. of Computing Science - University of Alberta
( / ) Edmonton, Alberta, Canada, T6G 2E8
\ O / Phone: (780)492-5411 Fax: (780)492-1071
\ / http://www.cs.ualberta.ca/~amaral
`----'
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