Q: Enabling not allowed outside wait?
A: Make the signal you are setting a registered signal instead of
combinatorial
Q: Is there a complete Pin out for the xs40?
A: sort of: look at the board manuals (xs40) (XSTends)
and this list
from EE 183 at Stanford.
Q: Why does a connected (I checked) wire have no load?
A: Make sure the destination uses the input. For example, the input
is in the signal list of a process() statement (in VHDL) or is used in a
state machine (eg. as a transition condition). If it is a clock input,
make sure you are specifying it that way (ie used in a if clk'event and
clk = '0')
Q: Why did one of the components I've made used for a while suddenly disapears, and I can't re-make it?
A: I don't know. FIX: create new project. copy component code to new
project, rename file and component to something new, then create the new
one with the new name in the new project.
Q: Why doesn't it do anything when I give keyboard input?
A1: Probably the wiring, connection (nets), state machine are broken. the keyboard input VHDL works.
A2: !!Make sure that reset is not raised!!
A3: Check the mapping report for removed/optimized away logic - see
it it is stuff you need (like your state machine).
Q: I want to see the implementation report that told what the errors were.
A: In project manager, on the right side go to the "reports" tab,
and dbl-click on "Implementation Log File".
Q: I got the source for a tutorial from the XESS book, but it does not work?
A: It is not implemented for the correct FPGA. To fix this, select
"Project -> Clear Implementation Data" from the project manager
menu. Now, re-implement, but before you click "run", be sure to select
the correct chip from the dropdown at the top of the dialog. Then it
--should-- work...
Q: Why does it asks for a license, and where do I get one?
A: If you are asked for a license, select "from file", and browse to
the "<drive>:\Xilinx\Data" directory, and select the "license.dat"
file. Check the "Save Settings" check box when prompted, so that
(hopefully) it will remember where the file is and not ask you again...
Q: How do you make a new version and keep the old one?
A1: on the versions tab in project manager, right click the project
and select "create version". You can also create revsion underneath each
version in the same way. WARNING: changes (ie to FSM, VHDL, schematic)
affect all versions!!
Q: "Implement" does not use changes in proj.ucf (and/or errors w/ netlist)?
A: Delete the current implementation from the "versions" tab in the
project manager.
Q: Why can't I use the D6 and D7 pins for parrallel port input (P32, P34)?
ERROR:OldMap:40 - Bad format for LOC constraint p22 on OPAD symbol "$I5/$1I63" (pad signal= S<2>). No such site for this device. This may also indicate
that a non-constrainable site (such as a VCC, GND, mode, configuration, or other special-purpose pin) has been used as a site name.
A1: These are forced to be I/O strobes for the parrallel port communication. You can't use them (exception, see A2).
A2: need to connect to them with "special" component MD0, MD2 so
they can be used for I/O.
Q: How do I make an Intel HEX file to download into the external RAM?
A: intelhex.pdf
(this is whitesheet direct form Intel.)
Q: Can I check the external RAM contents to see if my HEX file loaded properly?
Q: Can I get answers back out from external RAM?
A: use (at dos prompt):
xsload
-fpga <XS.bit> -ram <dumpfile.hex> -upload <start>
<length>
- start: first address to grab from
- length: number of bytes to dump
- dumpfile.hex: the output file (intel HEX format)
- XS.bit: any bit file for the FPGA being used - it is only needed so
that xsload know what chip it is interfacing with.
eg:
xsload -fpga lab.bit -ram dump.hex -upload 0 10
gets data from address 0 through 9 (10 bytes), puts it in local file
dump.hex.
Q: In the simulator, values on my bus (start ok, but then) go weird!
A: The simulator sometimes orders the bus lines in lexicographical order, so the lines are in the order (0,1,10,11,12,13,14,15,16,17,18,19,2,20,...). To fix this, select the bus. R-click and select bus->flatten. Drag-&-Drop the lines in the list to be a numerical order. The select all the lines, R-click and select bus->combine. If the numbers are still wierd, try selecting the bus and r-click, bus->change direction. This will reverse the order of the lines (swap MSB w/ LSB, and so on).
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