library IEEE;
use IEEE.std_logic_1164.all;

entity control is
    generic(
    	CNTMAX : integer := 25000000
    );
    port (
        clk: in STD_LOGIC;                       -- clk input (16 KHz)
        rst: in STD_LOGIC;                       -- reset input
        Addr: out integer range -1 to 65535;      -- integer representation of address
        data: in STD_LOGIC_VECTOR (7 downto 0);  -- input from the data lines of the RAM
        LLed: out STD_LOGIC_VECTOR (7 downto 0); -- ASCII output for the Left LED
        RLed: out STD_LOGIC_VECTOR (7 downto 0); -- ASCII output for the Right LED
        ALSel: out std_logic                     -- Address/LED Selection (0=Addr,1=LED)
    );
end control;

architecture control_arch of control is
                                
constant ADDRMAX : integer := 65536;                                       

signal lled_sig: std_logic_vector(7 downto 0);  -- Left LED internal buffer
signal rled_sig: std_logic_vector(7 downto 0);  -- Right LED internal buffer
signal cnt_signal: integer range 0 to CNTMAX;   -- clock divider counter
signal addr_sig : integer range 0 to ADDRMAX;


begin

LLed <= lled_sig;    -- output to left LED
RLed <= rled_sig;    -- output to right LED
Addr <= addr_sig; 
  -----------------------------------------------------------------------------
  -- ClockDivProcess: clock divider in which the clock cycle is maintained
  -----------------------------------------------------------------------------
 ClockDivProcess: process(clk, rst)
  begin
    if rst = '1' then                   -- reset counter on reset
      cnt_signal <= 0;
    elsif clk'event and clk = '1' then  -- clock divider counter
      if cnt_signal < CNTMAX then	-- this is not necessary for implementation but is
                                        -- necessary for the testbench
	  cnt_signal <= cnt_signal + 1;
      else
	  cnt_signal <= 0;
      end if;
    end if;
  end process;

  -----------------------------------------------------------------------------
  -- OutputControlProcess: based on the current place in the clock cycle,
  --                       signal assignments are made in this process
  -----------------------------------------------------------------------------
  OutputControlProcess: process(clk, rst)
  begin
    -- Default signal assignments.
    -- The default state for the system is to be displaying on the LEDs (not addressing RAM),
    -- not clocking the address counter and not changing the LED contents.
    -- Make the signal assignments that reflect this default state here.  (Hint: there are 4 assignments required)
    
    -- <<DEFAULT SIGNAL ASSIGNMENTS HERE>> --
    
    if rst = '1' then  -- clear LED buffers on reset

    -- <<RESET SIGNAL ASSIGNMENTS HERE>> --
    addr_sig <= 0;
    rled_sig<= X"00";
    lled_sig<= X"00";
    AlSel <= '1';

    elsif clk'event and clk='1' then
      case cnt_signal is
                   -- There are 4 stages in the RAM/LED cycle (ADDR, DATA, CLK, WAIT).
                   -- Fill in each stage with the correct signal assignments.
                   -- Remember that this is where the LED contents are buffered, so
                   -- you need to do the shifting from the right to the left somewhere
                   -- in this cycle as well.
                   
        -- ADDR: Set output as RAM address
        when 1 =>

        -- <<ADDR STAGE ASSIGNMENTS HERE>> --

        -- WAIT: hold the address and wait for data
        when 2 | 3 | 4 | 5 | 6 =>  

        -- <<WAIT STAGE ASSIGNMENTS HERE>> --

          
        -- DATA: Get RAM contents from Data lines
        when 7 =>
          
        -- <<DATA STAGE ASSIGNMENTS HERE>> --
		      

        -- CLK: Clock the Address Counter
        when 8 =>  

        -- <<CLK STAGE ASSIGNMENTS HERE>> --

          
        -- WAIT: keep things constant for the rest of the cycle
        when others =>
        
        -- <<WAIT STAGE ASSIGNMENTS HERE>> --
      end case;
    end if;
  end process;
  
end control_arch;