library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-------------------------------------------------------------------------------
-- This module implements an 2-to-1 multiplexer to choose between the arithmetic
--   and logic outputs.  The width of the data is determined by the generic
--   DATA_WIDTH.  This module is completely combinatorial.
-------------------------------------------------------------------------------

  entity mux is
    Generic (
      DATA_WIDTH : integer := 2
      );
    Port (
      selection : in  std_logic;
      inputA    : in  std_logic_vector(DATA_WIDTH-1 downto 0);
      inputB    : in  std_logic_vector(DATA_WIDTH-1 downto 0);
      output : out std_logic_vector(DATA_WIDTH-1 downto 0)
      );
  end mux;

  architecture mux_arch of mux is

  begin

    -------------------------------------------------------------------------
    -- SelectionProcess:
    --          Simple demonstration of the structure of a process.
    --          Selects the correct output
    -------------------------------------------------------------------------
    SelectionProcess: process(sel, inputA, inputB)
    begin
      if selection = '1' then
        output <= inputA;
      else
        output <= inputB;
      end if;
    end process;

  end mux_arch;