library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-------------------------------------------------------------------------------
-- This module implements an logic unit.  The width of the operands is
--   determined by the generic OPERAND_WIDTH.
-- Opcode width is fixed at 2 bits.

-- The output is synchronous (registered, produced on rising edge of clock).
-------------------------------------------------------------------------------


  entity logic_module is
    Generic (
      OPERAND_WIDTH : integer := 2
      );
    Port (
      operation: in  std_logic_vector(1 downto 0);
      operandA : in  std_logic_vector(OPERAND_WIDTH-1 downto 0);
      operandB : in  std_logic_vector(OPERAND_WIDTH-1 downto 0);
      result   : out std_logic_vector(OPERAND_WIDTH-1 downto 0)
      );
  end logic_module;

  architecture logic_module_arch of logic_module is

-- declare logical opcode constants
    constant opAND : std_logic_vector(1 downto 0) := "00";
    constant opOR  : std_logic_vector(1 downto 0) := "01";
    constant opXOR : std_logic_vector(1 downto 0) := "10";
    constant opNEG : std_logic_vector(1 downto 0) := "11";


  begin

-------------------------------------------------------------------------------
-- 	This process evaluates the operation specified by operation on the operands
--    operandA and operandB (or just operandA for unary operators).
-------------------------------------------------------------------------------
    EVAL_LOGIC: process(operandA, operandB, operation)
    begin
      case operation is
        -- perform and
        when opAND =>
          result <= operandA AND operandB;

					-- perform or				
        when opOR =>
          result <= operandA OR operandB;

					-- perform exclusive or				
        when opXOR =>
          result <= operandA XOR operandB;

					-- perform logical negation				
        when opNEG =>
          result <= NOT operandA;

					-- cover all cases not explicitly stated in case statement
        when others =>  
          result <= (others => '0');

      end case;
    end process EVAL_LOGIC;


  end logic_module_arch;