library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-------------------------------------------------------------------------------
-- This module encapsulates the ALU into a more general datapath.  In the CPU,
-- this datapath would include other components (in order to handle all
-- instructions that the CPU must respond to), but in our simple example, this
-- only involves registers to synchronize the ALU input and output
-------------------------------------------------------------------------------

  entity datapath is
    
    generic (
      OPERAND_WIDTH : integer);         -- data width

    port (
      clk      : in std_logic;
      rst      : in std_logic;
      operand1 : in std_logic_vector(OPERAND_WIDTH-1 downto 0);
      operand2 : in std_logic_vector(OPERAND_WIDTH-1 downto 0);
      opcode   : in std_logic_vector(2 downto 0);
      result   : out std_logic_vector(OPERAND_WIDTH-1 downto 0)
      );

  end datapath;


  architecture arch of datapath is

    component alu is
      Generic (
        OPERAND_WIDTH : integer
        );
      Port (
        -- The input/ouput interface of the module
        opcode   : in  std_logic_vector(2 downto 0);
        operand1 : in  std_logic_vector(OPERAND_WIDTH-1 downto 0);
        operand2 : in  std_logic_vector(OPERAND_WIDTH-1 downto 0);
        result   : out std_logic_vector(OPERAND_WIDTH-1 downto 0)
        );
    end component;

    
    component bit_reg is
      generic (
        DATA_WIDTH : integer);            -- width of register
      Port (
        clk      : in  std_logic;
        input    : in  std_logic_vector(DATA_WIDTH-1 downto 0);
        output   : out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
    end component;

    signal operand1_r : std_logic_vector(OPERAND_WIDTH-1 downto 0);
    signal operand2_r : std_logic_vector(OPERAND_WIDTH-1 downto 0);
    signal opcode_r : std_logic_vector(2 downto 0);
    
  begin  -- arch

    Operand1_reg: bit_reg
      generic map (
        DATA_WIDTH => OPERAND_WIDTH)
      port map (
        clk => clk,
        input  => operand1,
        output => operand1_r);

    Operand2_reg: bit_reg
      generic map (
        DATA_WIDTH => OPERAND_WIDTH)
      port map (
        clk => clk,
        input  => operand2,
        output => operand2_r);

    Opcode_reg: bit_reg
      generic map (
        DATA_WIDTH => OPERAND_WIDTH)
      port map (
        clk => clk,
        input  => opcode,
        output => opcode_r);

    Inst_ALU: alu
      generic map (
        OPERAND_WIDTH => OPERAND_WIDTH)
      port map (
        opcode   => opcode_r,
        operand1 => operand1_r,
        operand2 => operand2_r,
        result   => result);
      
  end arch;