Fine-Grain Stacked Register Allocation for the Itanium Architecture
Alban Douillet,
José Nelson Amaral,
Guang R. Gao
The introduction of a hardware managed register stack in the Itanium
Architecture creates an opportunity to optimize both the frequency in
which a compiler requests allocation of registers from this stack and
the number of registers requested. The Itanium Architecture specifies
the implementation of a Register Stack Engine (RSE) that automatically
performs register spills and fills. However, if the compiler requests
too many registers, through the alloc instruction, the RSE will be
forced to execute unnecessary spill and fill operations. In this paper
we introduce the formulation of the fine-grain register stack frame
sizing problem. The normal interaction between the compiler and
the RSE suggested by the Itanium Architecture designers is for the compiler to
request the maximum number of registers required by a procedure at the
procedure invocation. Our new problem formulation allows for more
conservative stack register allocation because it acknowledges that
the number of registers required in different control flow paths
varies significantly. We introduce a basic algorithm to solve the
stack register allocation problem, and present our preliminary
performance results from the implementation of our algorithm in the
Open64 compiler.
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