CMPUT329 - Fall 2003

TopicJ: Counters

José Nelson Amaral

Reading Material

Section 8.4 of Wakerly.

General Structure

A counter is a sequential circuit whose state diagram contains a single

cycle.

The modulus of a counter is the number of states in the cycle.

A counter with m states is called a module-m counter or a

divide-by-m counter.

Sm

S1

S2

S3

S4

S5

n-bit binary ripple counter

In a ripple counter, the carry information

ripples from the less significant to the

more significant bits.

Assume that the propagation delay from

T to Q in the flip-flops on the right is 10ns.

How long do we have to wait after a clock

input to read the value of the counter?

Is the waiting time dependent on the modulus

of the counter?

Synchronous Counters

In a synchronous counter,

all flip-flops are connected

to a common clock so that

all the outputs change

approximately at the same time.

However this synchronous counter

has a serial enable logic that

limits the speed of the clock.

A synchronous counter

with serial enable logic is

called a synchronous serial counter.

Synchronous Counters

A synchronous counter with

a parallel enable logic drives

each EN input with a dedicated

AND gate.

A synchronous counter

with parallel enable logic is

called a synchronous parallel counter.

The 74x163

The 74x163 is a synchronous 4-bit binary counter

with:

 active low load input

 active low clear input

When the load input is active and the clear

input is not active, then the value in the

inputs A, B, C, and D is loaded into the

counter.

RCO is the Ripple Carry Output. It is 1 when

all outputs QA, QB, QC, QD are 1 and the

enable input ENT is asserted.

74x163

74x163

A free-running 74x163

A counter is free-running when it counts continuously independent

of enable or clear inputs.

The following connections

convert the 74x163 into a

free-running, divide-by-16

counter

Quiz: How do you use the

74x163 to implement a

free-running divide-by-8 counter?

Free-running divide-by-16 counter waveforms

A Counter Quiz

Quiz: Use the 74x163 and any additional logic that you need

to implement a free-running divide-by-8 counter.

Counter Quiz #2

Quiz: Use the 74x163 and any additional logic that you need

to implement a free-running modulo-11 counter that counts the

sequence 5, 6, ..., 14, 15, 5, 6, ..., 14, 15, 5, 6, ....

Counter Quiz #2

Quiz: Use the 74x163 and any additional logic that you need

to implement a free-running modulo-11 counter that counts the

sequence 5, 6, ..., 14, 15, 5, 6, ..., 14, 15, 5, 6, ....

Counter Quiz #3

Quiz: Use the 74x163 and any additional logic that you need

to implement a free-running modulo-11 counter that counts the

sequence 0, 1, ..., 9, 10, 0, 1, ..., 9, 10, 0, 1, ....

Counter Quiz #3

Quiz: Use the 74x163 and any additional logic that you need

to implement a free-running modulo-11 counter that counts the

sequence 0, 1, ..., 9, 10, 0, 1, ..., 9, 10, 0, 1, ....

Cascading Counters

CLOCK, RESET_L, and LOAD_L are connected in parallel.

Cascading Counters

A master count-enable (CNTEN) is connect to the low order 74x163.

Cascading Counters

The RC04 output is asserted if and only if the low-order ‘163

is in state15 and CNTEN is asserted.

Cascading counters has the same ripple effect as a serial counter.

The maximum counting speed is limited by the propagation delay.

Quiz #4

Design a module-193 counter that counts from 63 to 255.

This counter should start counting when a GO_L input is

asserted.

When the counter reaches 255, it should stop and should

not re-start until GO_L is asserted again.

A module-193 Go-Counter.

When MAXCNT is

asserted, GO_L

controls the counter

A module-193 Go-Counter.

If GO_L is asserted,

The counter is reloaded

with 63. which

de-assert MAXCNT

Counting Direction

Sometimes we want to be able to select the direction of counting.

Design a module-4 counter with an up/dn input that controls the

direction of counting. If up/dn = 1 the counter counts up otherwise

it counts down.

0

2

1

3

up/dn=1

up/dn=1

up/dn=1

up/dn=1

up/dn=0

up/dn=0

up/dn=0

up/dn=0

Counting Direction

The 74x169 is a module-16 up/down counter

Decoding Binary-Counter States

By combining a binary counter with a decoder, we obtain a set of

1-out-of-m coded states.

Function Hazards
Different delays in the 138 cause glitches in the output

Glitch-free 1-out-of-m coded signals

CMPUT329 - Fall 2000

CMPUT329

Jose Nelson Amaral

1998-02-10T08:49:30