CMPUT329 - Fall 2003

TopicI: Building a Multicycle Data Path and a Control Path for a Microprocessor

José Nelson Amaral

Reading Material
(optional)

Patterson, David A., and Hennessy, John L., Computer

Organization & Design: The Hardware/Software Interface,

San Mateo, CA: Morgan Kaufmann Pub., 1994.

Chapter 5

Appendix B

Appendix C

What is Wrong with the Single Cycle Datapath

The clock cycle must have the same length for every instruction

Therefore the clock cycle cannot be shorter than the longest possible path

In our example, this path is the load instruction, it uses:

the instruction memory,

the register file,

the ALU,

the data memory, and

the register file.

What is Wrong with the Single Cycle Datapath

If we consider a machine with more complex instructions (p.e., floating-point arithmetics), or more powerful addressing modes, the single cycle penalty is unnaceptable.

The solution is to adopt a design with shorter clock cycles, but that requires multiple clock cycles per instruction.

M

u

x

0

1

M

u

x

0

1

M

u

x

0

1

2

3

PC

Sign

ext.

Shift

left 2

Read

address

Write

address

Write

data

MemData

Instruction

[31-26]

Instruction

[25-0]

Instruction

register

Memory

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

4

32

M

u

x

0

1

0

1

M

u

x

ALU

result

Zero

ALU

16

I[25-21]

I[20-16]

I[15-0]

[15-11]

A Multiple Cycle Datapath

The Jump Instruction

j loop

Concatenate the 4 most significant bits of the PC with the 26 least significant bits

of the IR[25-0] field of the instruction code and shift the result by two.

Write the resulting value in the PC.

PC  concat(PC[31-28],IR[25-0])<<2

2

10000

OpCode

address

000010

00 0000 0000 0001 0011 1001 0000

31 26

25 0

I-Type Instruction Format

Values to be written into the PC.

Three possible values can be written into the PC

according to the instruction executed:

For taken branches:

PC  PC + 4 + (sign-extend(IR[15-0]) << 2)

For jumps:

PC  concat(PC[31-28],IR[25-0])<<2

For all other instructions:

PC  PC + 4

Steps to Execute Each
Instruction Type

M

u

x

0

1

M

u

x

0

1

M

u

x

0

1

2

3

0

1

2

M

u

x

PC

Sign

ext.

Shift

left 2

Conc/

Shift

left 2

Read

address

Write

address

Write

data

MemData

Instruction

[31-26]

Instruction

[25-0]

Instruction

register

Memory

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

4

32

M

u

x

0

1

0

1

M

u

x

ALU

result

Zero

ALU

Target

16

4

26

32

I[25-21]

I[20-16]

I[15-0]

[15-11]

M

u

x

0

1

M

u

x

0

1

M

u

x

0

1

2

3

0

1

2

M

u

x

PC

Sign

ext.

Shift

left 2

Conc/

Shift

left 2

Read

address

Write

address

Write

data

MemData

Instruction

[31-26]

Instruction

[25-0]

Instruction

register

Memory

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

4

32

M

u

x

0

1

0

1

M

u

x

ALU

result

Zero

ALU

Target

16

32

TargetWrite

PCSource

ALU

control

IorD

MemWrite

MemRead

IRWrite

MemtoReg

ALUSelB

RegDst

RegWrite

ALUSelA

ALUOp

I[25-21]

I[20-16]

I[15-0]

[15-11]

4

26

32

PcWrite

M

u

x

0

1

M

u

x

0

1

M

u

x

0

1

2

3

0

1

2

M

u

x

PC

Sign

ext.

Shift

left 2

ALU

control

Conc/

Shift

left 2

Read

address

Write

address

Write

data

MemData

Instruction

[31-26]

Instruction

[25-0]

Instruction

register

Memory

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

4

32

M

u

x

0

1

0

1

M

u

x

ALU

result

Zero

ALU

Target

Control

Unit

16

4

26

32

PcWrite

PcWriteCond

IorD

MemWrite

MemRead

IRWrite

MemtoReg

ALUSelB

RegDst

RegWrite

TargetWrite

ALUSelA

PCSource

ALUOp

I[25-21]

I[20-16]

I[15-0]

[15-11]

32

Designing the Control Unit for the Multicycle Datapath

Instruction

Fetch

Instruction

Decode

Address

Computation

Execution

Jump

Completion

Branch

Completion

Memory

Read

Memory

Write

R-Type

Completion

Write

Back

Load + Store

R-type

Branch

Jump

Load

Store

MemRead

ALUSelA=0

IorD=0

IRWrite

ALUSelB=01

ALUOp=00

PCWrite

PCSource=00

ALUSelA=0

ALUSelB=11

ALUOp=00

TargetWrite

ALUSelA=1

ALUSelB=10

ALUOp=00

ALUSelA=1

ALUSelB=00

ALUOp=10

PCWrite

PCSource=10

ALUSelA=1

ALUSelB=00

ALUOp=01

PCWriteCond

PCSource=01

MemRead

ALUSelA=1

IorD=1

ALUSelB=10

ALUOp=00

MemWrite

ALUSelA=1

IorD=1

ALUSelB=10

ALUOp=00

ALUSelA=1

RegDst=1

RegWrite

MemtoReg=0

ALUSelB=0

ALUOp=10

MemRead

ALUSelA=1

IorD=1

RegWrite

MemtoReg=1

RegDst=0

ALUSelB=10

ALUOp=00

Load + Store

R-type

Branch

Jump

Load

Store

Conventions

All outputs that are not explictly asserted, are

de-asserted, i.e., they must be specified for the

correct operation of the datapath.

If a signal that controls a multiplexor is not specified

in a state, its value is don’t care, and the machine

will work properly regardless of the input that is

selected.

Finite State Machine Controller

State Register

Input from Instruction

Register Opcode Field

17 Datapath

Control Outputs

21 Outputs

10 Inputs

Combinatorial

Control Logic

CMPUT329 - Fall 2000

CMPUT329

Jose Nelson Amaral

1998-02-10T08:49:30

Trial User