CMPUT329 - Fall 2003

TopicH: Building a Data Path and a Control Path for a Microprocessor

José Nelson Amaral

A Sample Problem

The following is a legal add instruction in the MIPS microprocessor:

ADD $s1, $s2, $s3

How is the addition of two integers

constructed from these three basic operations?

We know that all the functions of a digital

computer are implemented from three

basic logic operations: AND, OR, and NOT.

Representing Instructions: R-Type Instructions

add $8, $17, $18

This instruction has 3 operands. The data that is operates on is stored in registers.

It adds the content of registers $17 and $18 and stores the result

in register $8. Its meaning can be summarized as follows:

$8  $17 + $18

000000

10001

10010

01000

00000

100000

31 26

5 0

10 6

15 11

20 16

25 21

0

17

18

8

0

32

OpCode

rs

rt

Destination

shiftamt

function

R-Type Instruction Format

Representing Instructions: Memory Instructions

lw $7, 68($9)

Read the memory location addressed by the value in register $9 plus 68

and store the value in register $7

Its meaning can be summarized as follows:

$7  Memory[$9 + 68]

100001

01001

00111

0000000001000100

31 26

15 0

20 16

25 21

35

9

7

68

OpCode

rs

rt

address

I-Type Instruction Format

Representing Instructions:
Memory Instructions

sw $13, 56($17)

Write the value currently in register $13 in the memory location addressed by

the value in register $17 plus 56

Its meaning can be summarized as follows:

Memory[$17 + 56]  $13

101011

10001

01101

0000000000111000

31 26

15 0

20 16

25 21

43

17

13

56

OpCode

rs

rt

address

I-Type Instruction Format

Representing Instructions:
Branch Instructions

bne $1, $2, 100

Add 4 to the PC. If the value in register $1 is not equal the value in register $2,

then add 100 to the PC before fetching the next instruction.

Its meaning can be summarized as follows:

PC  PC + 4

if($1  $2) PC  PC + 100

000101

00001

00010

0000000001100100

31 26

15 0

20 16

25 21

5

1

2

100

OpCode

rs

rt

address

I-Type Instruction Format

Building a Datapath:
Instruction Memory

Read

address

Instruction

Memory

PC

Sum

Adder

Write

Program Counter

Instruction Memory

Adder

Building a Datapath
PC Incrementer

Read

address

Instruction

Memory

Sum

Adder

PC

Write

4

Building a Data Path
Register File and ALU

ALU

result

Zero

ALU

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

5

5

5

32

Register File

ALU

32

32

Data

ALU operation

RegWrite

A Two Read Port File with n Registers

Reg. 0

Reg. 1

•••

Reg. n-2

Reg. n-1

5-to-32

decoder

RegWrite

M

u

x

M

u

x

Read

Register 1

Read

Register 2

Write

Data

Write

Register

C

D

C

D

C

D

C

D

C

D

32

32

Reg. 0

Reg. 1

M

u

x

Read

Register 1

32

Read

Register 1

M

u

x

1

R0_0

R1_0

R31_0

M

u

x

1

R0_1

R1_1

R31_1

M

u

x

1

R0_31

R1_31

R31_31

•••

•••

•••

R31

R0

R1

5

Building a Data Path
R-Type Instruction

0

17

18

8

0

32

OpCode

rs

rt

Destination

shiftamt

function

000000

10001

10010

01000

00000

100000

31 26

5 0

10 6

15 11

20 16

25 21

add $8, $17, $18

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

32

32

ALU

result

Zero

ALU

ALU operation

Instruction

I(25-21)

I(15-11)

I(20-16)

RegWrite

Building a Data Path
Load/Store Instructions

Read

address

Write

address

Write

data

MemData

Data

Memory

MemWrite

MemRead

Data Memory Unit

Sign

ext.

16

32

Sign-extension Unit

Building a DataPath
Load/Store Instructions

100001

01001

00111

0000000001000100

31 26

15 0

20 16

25 21

35

9

7

68

OpCode

rs

rt

address

lw $7, 68($9)

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

32

ALU

result

Zero

ALU

ALU operation

Read

address

Write

address

Write

data

MemData

Data

Memory

MemRead

Sign

ext.

RegWrite

32

16

Instruction

I(25-21)

I(20-16)

Building a DataPath
Load/Store Instructions

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

ALU

result

Zero

ALU

ALU operation

Read

address

Write

address

Write

data

MemData

Data

Memory

MemWrite

Sign

ext.

32

sw $13, 56($17)

43

17

13

56

OpCode

rs

rt

address

101011

10001

01101

0000000000111000

31 26

15 0

20 16

25 21

16

Instruction

I(25-21)

32

I(20-16)

Combining Memory and Register Instr. Datapaths

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

32

Instruction

Read

address

Write

address

Write

data

MemData

Data

Memory

MemWrite

MemRead

Sign

ext.

16

ALU

result

Zero

ALU

ALU operation

RegWrite

sw $13, 56($17)

43

17

13

56

OpCode

rs

rt

address

0

1

M

u

x

32

M

u

x

0

1

32

ALUSrc

MemtoReg

add $8, $17, $18

0

17

18

8

0

32

OpCode

rs

rt

Destination

shiftamt

function

Building a DataPath
Branch Instructions

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

Zero

ALU

ALU operation

Instruction

Sign

ext.

32

32

16

bne $1, $2, 100

5

1

2

100

OpCode

rs

rt

address

000101

00001

00010

0000000001100100

31 26

15 0

20 16

25 21

Sum

Adder

PC + 4

Shift

left 2

Branch

Target

To branch

control logic

I(25-21)

I(20-16)

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

32

32

Instruction

Read

address

Write

address

Write

data

MemData

Data

Memory

MemWrite

MemRead

16

32

ALU

result

Zero

ALU

RegWrite

0

1

M

u

x

M

u

x

0

1

ALUSrc

MemtoReg

Read

address

Instruction

Memory

Sum

Adder

PC

Write

4

Sum

Adder

Shift

left 2

0

1

M

u

x

PCSrc

Sign

ext.

ALU

control

I(5-0)

Destination Register for Load and R-Type Instr.

35

9

7

68

OpCode

rs

rt

address

lw $7, 68($9)

0

17

18

8

0

32

OpCode

rs

rt

Destination

shiftamt

function

add $8, $17, $18

The Destination register of a load is specified in

I20-I16, but for an R-Type instruction the destination

is specified by the bits I15-I11. Therefore we need

a multiplex in the data path of the write register.

31 26

15 0

20 16

25 21

31 26

5 0

10 6

15 11

20 16

25 21

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

32

32

Read

address

Write

address

Write

data

MemData

Data

Memory

MemWrite

MemRead

16

32

ALU

result

Zero

ALU

RegWrite

0

1

M

u

x

M

u

x

0

1

I(25-21)

I(20-16)

I(15-11)

ALUSrc

MemtoReg

Read

address

Instruction

Memory

Sum

Adder

PC

Write

4

Sum

Adder

Shift

left 2

0

1

M

u

x

PCSrc

M

u

x

0

1

RegDst

I(15-0)

Sign

ext.

ALU

control

ALUOp

I(5-0)

Four Steps of an R-type Instruction

1. Fetch Instruction from instruction memory, and increment PC.

2. Read two registers (I25-I21) and (I20-I16) from the register file.

3. Use bits I5-I0 from the instruction code to determine the

function that the ALU performs on the data read from

the register file.

4. Write the ALU result to the destination register (I15-I11).

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

32

32

Read

address

Write

address

Write

data

MemData

Data

Memory

MemWrite

MemRead

16

32

ALU

result

Zero

ALU

RegWrite

0

1

M

u

x

M

u

x

0

1

I(25-21)

I(20-16)

I(15-11)

ALUSrc

MemtoReg

Read

address

Instruction

Memory

Sum

Adder

PC

Write

4

Sum

Adder

Shift

left 2

0

1

M

u

x

PCSrc

M

u

x

0

1

RegDst

R-Type Instruction

First Step: Instruction Fetch

Sign

ext.

ALU

control

ALUOp

I(5-0)

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

32

32

Read

address

Write

address

Write

data

MemData

Data

Memory

MemWrite

MemRead

16

32

ALU

result

Zero

ALU

RegWrite

0

1

M

u

x

M

u

x

0

1

I(25-21)

I(20-16)

I(15-11)

ALUSrc

MemtoReg

Read

address

Instruction

Memory

Sum

Adder

PC

Write

4

Sum

Adder

Shift

left 2

0

1

M

u

x

PCSrc

M

u

x

0

1

RegDst

R-Type Instruction

Second Step: Read Source Registers

Sign

ext.

ALU

control

ALUOp

I(5-0)

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

32

32

Read

address

Write

address

Write

data

MemData

Data

Memory

MemWrite

MemRead

16

32

ALU

result

Zero

ALU

RegWrite

0

1

M

u

x

M

u

x

0

1

I(25-21)

I(20-16)

I(15-11)

ALUSrc

MemtoReg

Read

address

Instruction

Memory

Sum

Adder

PC

Write

4

Sum

Adder

Shift

left 2

0

1

M

u

x

PCSrc

M

u

x

0

1

RegDst

R-Type Instruction

Third Step: ALU Operates on Registers

Sign

ext.

ALU

control

ALUOp

I(5-0)

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

32

32

Read

address

Write

address

Write

data

MemData

Data

Memory

MemWrite

MemRead

16

32

ALU

result

Zero

ALU

RegWrite

0

1

M

u

x

M

u

x

0

1

I(25-21)

I(20-16)

I(15-11)

ALUSrc

MemtoReg

Read

address

Instruction

Memory

Sum

Adder

PC

Write

4

Sum

Adder

Shift

left 2

0

1

M

u

x

PCSrc

M

u

x

0

1

RegDst

R-Type Instruction

Final Step: Write the Result

Sign

ext.

ALU

control

ALUOp

I(5-0)

Four Steps for a load Instruction

1. Fetch Instruction from instruction memory, and increment PC.

2. Read one register (I25-I21) from the register file.

3. The ALU computes the sum of the value read from the register

file and the sign-extended lower 16 bits of the instruction (offset).

4. Use the result of the ALU as an address to the data memory.

5. Write the data from the memory unit to the destination

register (I20-I16).

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

32

32

Read

address

Write

address

Write

data

MemData

Data

Memory

MemWrite

MemRead

16

32

ALU

result

Zero

ALU

RegWrite

0

1

M

u

x

M

u

x

0

1

I(25-21)

I(20-16)

I(15-11)

ALUSrc

MemtoReg

Read

address

Instruction

Memory

Sum

Adder

PC

Write

4

Sum

Adder

Shift

left 2

0

1

M

u

x

PCSrc

M

u

x

0

1

RegDst

DataPath for a Load Instruction

Sign

ext.

ALU

control

ALUOp

I(5-0)

Four Steps for a branch-on-equal Instruction

1. Fetch Instruction from instruction memory, and increment PC.

2. Read two registers (I25-I21) and (I20-I16) from the register file.

3. The ALU subtracts the data values read from the register.

Add the value PC + 4 to the sign-extended lower 16 bits

of the instruction (offset) --- the result is the branch target.

4. Use the zero result from the ALU to decide which adder result

to store in the PC (either the branch target or PC+4).

Read

register 1

Read

register 2

Write

register

Write

data

Read

data 1

Read

data 2

Registers

32

32

32

Read

address

Write

address

Write

data

MemData

Data

Memory

MemWrite

MemRead

16

32

ALU

result

Zero

ALU

RegWrite

0

1

M

u

x

M

u

x

0

1

I(25-21)

I(20-16)

I(15-11)

ALUSrc

MemtoReg

Read

address

Instruction

Memory

Sum

Adder

PC

Write

4

Sum

Adder

Shift

left 2

0

1

M

u

x

PCSrc

M

u

x

0

1

RegDst

DataPath for a Branch Instruction

Sign

ext.

ALU

control

ALUOp

Branch

I(5-0)

ALU Control

ALU

control

ALUOp

I(5-0)

ALU Control Input

ALU Control

ALU

control

ALUOp

I(5-0)

ALU Control Input

Function

Code

ALU Control

I2 = ALUOp0 + ALUOp1.F1

010

Op1

110

X

Op0

F3

010

110

X

X

001

000

111

X

X

X

X

X

X

X

X

X

F1

F2

F0

ALU Control

F3

010

110

X

X

001

000

111

X

X

X

X

X

X

X

X

X

F1

F2

F0

010

Op1

110

X

Op0

I1 = ALUOp1’ + ALUOp1.F2’

ALU Control

I0 = ALUOp1.F3 + ALUOp1.F0

F3

010

110

X

X

001

000

111

X

X

X

X

X

X

X

X

X

F1

F2

010

Op1

110

X

Op0

ALU Control Unit

I2 = ALUOp0 + ALUOp1.F1

I1 = ALUOp1’ + ALUOp1.F2’

I0 = ALUOp1.F3 + ALUOp1.F0 = ALUOp1.(F3+F0)

ALU

control

ALUOp

I(5-0)

ALU Control Input

Function

Code

ALUOp

ALU

Control

Input

Function

Code

F(5-0)

F1

F2

F3

F0

ALUOp0

ALUOp1

ALUOp1

ALUIn2

ALUIn1

ALUIn0

Main Control Unit

CMPUT329 - Fall 2000

CMPUT329

Jose Nelson Amaral

1998-02-10T08:49:30

Trial User