CMPUT329 - Fall 2003

Topic: Internal Organization of an FPGA

José Nelson Amaral

Source Material

Xilinx, Spartan II 2.5V FPGA Family: Functional

Description, Sept. 2003

Xilinx, Spartan II 2.5V FPGA Family: Introduction

and Ordering Information, Sept. 2003

Basic Spartan-II FPGA Block Diagram

Input/Output Blocks

(IOBs) interface

between the package

pins and the internal logic.

Configurable Logic Blocks

(CLBs) provide the

functional elements

to implement most of

the logic.

Delay-Locked Loops

(DLLs) distribute

the clock and

properly compensate

for delays.

Block RAMs

each has 4096 bits.

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

TFF

OFF

IFF

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

IOB Registers may be:

 edge-triggered D-type flip-flops

 level-sensitive latches

TFF

OFF

IFF

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

A clock signal is shared by the three registers.

TFF

OFF

IFF

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

Each register has an independent clock enable.

TFF

OFF

IFF

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

The three registers share a

Set/Reset (SR) line.

TFF

OFF

IFF

 synchronous Set

 synchronous Reset

 asynchronous Preset

 asynchronous Clear

The SR input can be

independently configured

in each register as:

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

TFF

OFF

IFF

The I/O buffers and all control signals have independent polarity controls.

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

TFF

OFF

IFF

Input Path: The IOB routes an input signal either directly

or through an optional input flip-flop.

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

TFF

OFF

IFF

Input Path: The IOB routes an input signal either directly

or through an optional input flip-flop.

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

TFF

OFF

IFF

Input Path: The optional delay eliminates pad-to-pad hold time.

The delay matches the internal clock distribution delay of the FPGA,

assuring that the pad-to-pad hold time is zero.

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

TFF

OFF

IFF

Output path: a three-state output buffer drives the signal onto the pad.

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

TFF

OFF

IFF

Output path: the output signal can be routed directly to the buffer

or through an optional IOB output flip-flop.

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

TFF

OFF

IFF

Output path: the output signal can be routed directly to the buffer

or through an optional IOB output flip-flop.

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

TFF

OFF

IFF

Output path: the three-state control of the output

can also be routed directly to the buffer

or through an optional IOB output flip-flop.

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

TFF

OFF

IFF

Output path: the three-state control of the output

can also be routed directly to the buffer

or through an optional IOB output flip-flop.

SR

Q

D

CK

EC

SR

Q

D

CK

EC

SR

Q

D

CK

EC













T

CLK

TCE

SR

O

OCE

IQ

I

ICE

VCC

Programmable

Output Buffer

Programmable

Delay

Programmable

Input Buffer

Programmable

Bias &

ESD Network

Package Pin

Package

Pin





Internal

Reference

Package Pin



To Next I/O

To Other

External VREF Inputs

of Bank

Spartan-II Input/Output Block (IOB)

TFF

OFF

IFF

All pads are protected against damage from electrostatic discharge (ESD)

and from over-voltage transients.

SR

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

F5IN

BY

COUT

YB

Y

YQ

I4

I3

I2

I1

O

CLK

CE

CIN

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

BX

XB

X

XQ

I4

I3

I2

I1

O

Spartan-II CLB Slice

Each slice has two

identical

logic cells (LC)

A Configurable Logic Block

(CLB) has two

identical slices

SR

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

F5IN

BY

COUT

YB

Y

YQ

I4

I3

I2

I1

O

CLK

CE

CIN

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

BX

XB

X

XQ

I4

I3

I2

I1

O

Spartan-II CLB Slice

A logic cell has a

4-input function generator,

carry logic and an

storage element.

The output from the

function generator

drives the CLB output

and the D input of

the flip-flop.

A CLB also contains logic to

combine function generators

to provide functions of five

or six inputs.

Look-Up Tables

A Look-Up Table is a 161 RAM. It can be used as a

function generator for any logic function with up to 4

Inputs and one output

In the Spartan-II, an LUT can also provide

the functionality of:

a 16 1-bit synchronous RAM

A 16-bit shift register

An LUT Function Generator

1

1

0

1

0

1

1

1

1

1

1

1

1

1

1

0

0

1

0

1

1

1

1

0

0

0

0

1

1

1

0

0

1

1

1

1

1

1

0

0

0

1

0

1

1

0

0

0

1

0

1

1

0

0

0

0

0

0

1

1

0

0

1

0

0

1

1

1

0

0

1

1

1

0

1

0

0

0

1

1

1

1

1

0

0

0

0

1

0

1

0

0

0

1

1

1

1

1

0

0

0

1

0

0

1

…

0

1

1

0

0

1

0

0

0

0

0

0

0

0

1

…

0

1

1

1

0

1

1

1

0

1

1

1

1

1

0

…

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

0

0

0

1

1

1

1

0

0

0

1

0

1

0

0

0

1

1

0

1

1

0

0

0

0

0

0

1

0

0

0

0

0

0

1

1

1

0

0

1

1

1

0

0

0

0

1

0

1

1

1

1

0

0

0

0

1

0

0

0

0

1

1

1

1

1

1

0

0

0

1

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

EQ4

EQ3

XOR4

XOR3

XOR2

OR4

OR3

OR2

AND4

AND3

AND2

I1

I2

I3

I4

SR

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

F5IN

BY

COUT

YB

Y

YQ

I4

I3

I2

I1

O

CLK

CE

CIN

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

BX

XB

X

XQ

I4

I3

I2

I1

O

Spartan-II CLB Slice

The storage element

can be configured as:

 edge-triggered D flip-flop

 level-sensitive latch.

SR

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

F5IN

BY

COUT

YB

Y

YQ

I4

I3

I2

I1

O

CLK

CE

CIN

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

BX

XB

X

XQ

I4

I3

I2

I1

O

Spartan-II CLB Slice

The D input can be driven

by the function generator

or directly from the slice

inputs.

SR

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

F5IN

BY

COUT

YB

Y

YQ

I4

I3

I2

I1

O

CLK

CE

CIN

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

BX

XB

X

XQ

I4

I3

I2

I1

O

Spartan-II CLB Slice

The D input can be driven

by the function generator

or directly from the slice

inputs.

SR

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

F5IN

BY

COUT

YB

Y

YQ

I4

I3

I2

I1

O

CLK

CE

CIN

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

BX

XB

X

XQ

I4

I3

I2

I1

O

Spartan-II CLB Slice

The FF receive the same

clock signal.

SR

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

F5IN

BY

COUT

YB

Y

YQ

I4

I3

I2

I1

O

CLK

CE

CIN

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

BX

XB

X

XQ

I4

I3

I2

I1

O

Spartan-II CLB Slice

Each slice has synchronous

set and reset signals

SR forces a storage

element into

the initialization state

specified for it

in the configuration

SR

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

F5IN

BY

COUT

YB

Y

YQ

I4

I3

I2

I1

O

CLK

CE

CIN

Look-Up

Table

Carry

and

Control

Logic

S

Q

D

CK

EC

R

G4

G3

G2

G1

BX

XB

X

XQ

I4

I3

I2

I1

O

Spartan-II CLB Slice

Each slice has synchronous

set and reset signals

SR forces a storage

element into

the initialization state

specified for it

in the configuration

BY forces it

into the opposite

state.

SR and BY can be configured to work asynchronously.

Basic Spartan-II FPGA Block Diagram

Input/Output Blocks

(IOBs) interface

between the package

pins and the internal logic.

Configurable Logic Blocks

(CLBs) provide the

functional elements

to implement most of

the logic.

Delay-Locked Loops

(DLLs) distribute

the clock and

properly compensate

for delays.

Block RAMs

each has 4096 bits.

CMPUT329 - Fall 2000

CMPUT329

Jose Nelson Amaral

1998-02-10T08:49:30

Trial User