CMPUT329 - Fall 2003

TopicE: Clock Skew and Clock Gating

José Nelson Amaral

Timing With
Propagation Delays

Clock Skew

Clock signal may not reach all flip-flops simultaneously.

Output changes of flip-flops receiving “early” clock may reach D inputs of flip-flops with “late” clock too soon.

Clock Skew

Reasons for slowness:
(a) wiring delays

(b) capacitance

(c) incorrect design

Clock-skew calculation

tffpd(min) + tcomb(min)  thold  tskew(max) > 0

First two terms are minimum time after clock edge for a D input to change

Hold time is earliest time that the input may change

Clock skew subtracts from the available
hold-time margin

Compensating for clock skew:

Longer flip-flop propagation delay

Explicit combinational delays

Shorter (even negative) flip-flop hold times

Example of bad clock distribution

Clock distribution in ASICs

This is what a typical ASIC router will do if you don’t lay out the clock by hand.

“Clock-tree” solution

Often laid out by hand

Wide,fast metal (low R ==> fast RC time constant)

Gating the clock

Definitely a no-no

Glitches possible if control signal (CLKEN) is generated by the same clock

Excessive clock skew in any case.

If you really must gate the clock...

CMPUT329 - Fall 2000

CMPUT329

Jose Nelson Amaral

1998-02-10T08:49:30