CMPUT329 - Fall 2003
Reading Assignment
Gate Delays and Time Diagrams
Oscillating Circuit
Slide 5
Bistable element
Analog analysis
Metastability
Slide 9
Slide 10
Another look at metastability
Why all the harping on metastability?
Back to the bistableÉ.
The Set-Reset Latch
Slide 15
Slide 16
Slide 17
Slide 18
Slide 19
Slide 20
Slide 21
S-R latch operation
S-R latch timing parameters
S-R latch symbols
S-R latch using NAND gates
S-R latch with enable
Using an enable S-R latch to build a Trigger Latch
D latch
D-latch operation
D-latch timing parameters
Edge-triggered D flip-flop behavior
Slide 32
D flip-flop timing parameters
Other D flip-flop variations
J-K flip-flops
Author: Jose Nelson Amaral
E-mail: amaral@cs.ualberta.ca
Homepage: http://www.cs.ualberta.ca/~amaral/courses/329