ylibrary IEEE; use IEEE.std_logic_1164.all; entity Lab2 is port ( CLK: in STD_LOGIC; PSCLK: in STD_LOGIC; PSDATA: in STD_LOGIC; RST_L: in STD_LOGIC; HEX: out STD_LOGIC_VECTOR (3 downto 0); P: out STD_LOGIC_VECTOR (6 downto 0) ); end Lab2; architecture Lab2_arch of Lab2 is component KB_INPUT is port ( clk: in std_logic; -- main clock rst: in std_logic; -- reset psClk: in std_logic; -- keyboard clock psData: in std_logic; -- keyboard data scancode: out std_logic_vector(7 downto 0); -- key scancode rdy: out std_logic; -- scancode ready pulse ); end component KB_INPUT; component SC_HEX is port ( sc: in std_logic_vector(7 downto 0); prs : in std_logic; hex : out std_logic_vector(3 downto 0) ); end component SC_HEX; component PARITY is port ( HEX: in STD_LOGIC_VECTOR (3 downto 0); LED: out STD_LOGIC_VECTOR (6 downto 0) ); end component PARITY; component IBUF is port ( i: in std_logic; o: out std_logic ); end component IBUF; attribute box_type : string; attribute box_type of IBUF : component is "black_box"; signal rst, rdy : std_logic; signal PSCLK_buf: std_logic; signal sc: std_logic_vector(7 downto 0); signal P_H : std_logic_vector(6 downto 0); signal hex_signal : std_logic_vector(3 downto 0); begin -- <> rst <= ; Inst_ibuf: IBUF port map (PSCLK, psClk_buf); input: KB_INPUT port map ( clk=>, rst=>, psclk=>, psData=>, scancode=>, rdy=>); kb_hex_mod: SC_HEX port map (sc=>, prs=>, hex=>); parity_mod: PARITY port map (HEX=>, LED=>); hex <=; P <= ; end Lab2_arch;