-- serialize sine wave samples from SINGEN for output to the stereo codec

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity serializer is
    port (
        D: in STD_LOGIC_VECTOR (7 downto 0);
        clk: in STD_LOGIC;
        S: out STD_LOGIC;
        SClk: out STD_LOGIC;
        MClk: out STD_LOGIC;
        lr: out std_logic;
        rst: in std_logic
    );
end serializer;

architecture serializer_arch of serializer is

constant MAXCNT : integer := 19;  -- max number of bits - 1
constant CHLEN : integer := 127;
constant LEFT: std_logic := '1';
constant RIGHT: std_logic := '0';

--signal bitcnt : integer range 0 to MAXCNT;
signal lrsel: std_logic;
signal lencnt: integer range 0 to CHLEN;
signal data : std_logic_vector(MAXCNT downto 0);
signal Mclock: std_logic;
signal cnt: std_logic_vector(3 downto 0);

begin

S <= not data(MAXCNT);  -- use MSB as serial data out
lr <= lrsel;
MClk <= not cnt(1);
MClock <= not cnt(1);
SClk <= not cnt(3);

  process(clk, rst)
  begin
    if rst = '1' then
      cnt <= "0000";
    elsif clk'event and clk = '1' then
      cnt <= cnt+1;
    end if;
  end process;

  process(rst, MClock, D)
  begin
    if rst = '1' then
--      bitcnt <= 0;
      lencnt <= 0;
      lrsel <= LEFT;
      data <= (others=>'0');
    elsif MCLock'event and MClock = '0' then  -- clk on 0 due to inverters on xstends board
      if lencnt = 0 then
        -- set counters
--        bitcnt <= MAXCNT;
        lencnt <= CHLEN;
        lrsel <= not lrsel;
        -- get data
				data(MAXCNT downto 7) <= (others=>D(7));   -- sign extension from the 8-bit input to 20-bit output
        data(6 downto 0) <= D(6 downto 0);         -- input data goes to lower bits
      else
        lencnt <= lencnt - 1;
--        bitcnt <= bitcnt - 1;
        data <= data(MAXCNT-1 downto 0) & '0';  -- shift data out MSB first
      end if;
    end if;
  end process;
  
end serializer_arch;