library IEEE;
use IEEE.std_logic_1164.all;

entity LineSel is
    port (
        LLed: in STD_LOGIC_VECTOR (7 downto 0);  -- input for left LED
        RLed: in STD_LOGIC_VECTOR (7 downto 0);  -- input for right LED
        Addr: in STD_LOGIC_VECTOR (15 downto 0); -- input for RAM address
        rst: in std_logic;                       -- reset
        clk: in std_logic;                       -- clk
        A: out STD_LOGIC_vector(15 downto 0);    -- output on LED/Address lines
        ALSel: in STD_LOGIC                      -- input for Address/Led Selection (0=Addr,1=LED)
    );
end LineSel;

architecture LineSel_arch of LineSel is
begin

  process(ALSel, LLed, RLed, Addr, clk, rst)
  begin
    if rst = '1' then
      A <= (others => '1');  -- clear the LED contents on reset (active-low)
    elsif clk'event and clk = '1' then
      if ALSel = '1' then
      
      -- <<insert code for LED display output here>> --
        
      else
      
      -- <<insert code for RAM address output here>> --

      end if;
    end if;
  end process;

end LineSel_arch;