library IEEE; use IEEE.std_logic_1164.all; entity control is port ( clk: in STD_LOGIC; -- clk input (16 KHz) rst: in STD_LOGIC; -- reset input Addrclk: out STD_LOGIC; -- output to clock the address counter data: in STD_LOGIC_VECTOR (7 downto 0); -- input from the data lines of the RAM LLed: out STD_LOGIC_VECTOR (7 downto 0); -- output for the Left LED RLed: out STD_LOGIC_VECTOR (7 downto 0); -- output for the Right LED ALSel: out std_logic -- Address/LED Selection (0=Addr,1=LED) ); end control; architecture control_arch of control is constant CNTMAX: integer := 8000; -- LED/Address cycle length. -- Larger = slower system (letters stay on LED longer) signal L: std_logic_vector(7 downto 0); -- Left LED internal buffer signal R: std_logic_vector(7 downto 0); -- Right LED internal buffer signal cnt: integer range 0 to CNTMAX; -- clock divider counter begin LLED <= L; -- output to left LED RLED <= R; -- output to right LED -- clock divider process(clk, rst) begin if rst = '1' then -- reset counter on reset cnt <= 0; elsif clk'event and clk = '1' then -- clock divider counter cnt <= cnt + 1; end if; end process; -- output control process(cnt, rst, data, L, R) begin if rst = '1' then -- clear LED buffers on reset -- <> -- else case cnt is -- There are 4 stages in the RAM/LED cycle. -- Fill in each stage with the correct signal assignments. -- Things that need to be accomplished (not necessarily in this order): -- Set the RAM address as output -- Increment the RAM address counter (raise addrclk) -- Read the new character from the RAM output -- In connection to reading the new char, shift the current char from right to left LED -- set output to CHARs for the LEDs for the rest of the time -- Remember that this module is where the LED contents are buffered, so -- you need to do the shifting from the right to the left somewhere -- in this cycle. Also remember that all the statements (including signal -- assignments) are executed concurrently, not sequentially. Hint: This is why we -- need 3 and not 2 steps. -- step 1 when 1 => -- step 2 when 2 => -- step 3 when 3 => -- default values for output for the rest of the time when others => end case; end if; end process; end control_arch;