library IEEE;
use IEEE.std_logic_1164.all;

entity control is
    port (
        clk: in STD_LOGIC;                       -- clk input (16 KHz)
        rst: in STD_LOGIC;                       -- reset input
        Addrclk: out STD_LOGIC;                  -- output to clock the address counter
        data: in STD_LOGIC_VECTOR (7 downto 0);  -- input from the data lines of the RAM
        LLed: out STD_LOGIC_VECTOR (7 downto 0); -- output for the Left LED
        RLed: out STD_LOGIC_VECTOR (7 downto 0); -- output for the Right LED
        ALSel: out std_logic                     -- Address/LED Selection (0=Addr,1=LED)
    );
end control;

architecture control_arch of control is

constant CNTMAX: integer := 8000;        -- LED/Address cycle length.
                                         -- Larger = slower system (letters stay on LED longer)

signal L: std_logic_vector(7 downto 0);  -- Left LED internal buffer
signal R: std_logic_vector(7 downto 0);  -- Right LED internal buffer
signal cnt: integer range 0 to CNTMAX;   -- clock divider counter

begin

LLED <= L;    -- output to left LED
RLED <= R;    -- output to right LED
  
  
  -- clock divider
  process(clk, rst)
  begin
    if rst = '1' then                   -- reset counter on reset
      cnt <= 0;
    elsif clk'event and clk = '1' then  -- clock divider counter
      cnt <= cnt + 1;
    end if;
  end process;
  
  
  -- output control
  process(cnt, rst, data, L, R)
  begin
    -- Default signal assignments.
    -- The default state for the system is to be displaying on the LEDs (not addressing RAM),
    -- not clocking the address counter and not changing the LED contents.
    -- Make the signal assignments that reflect this default state here.  (Hint: there are 4 assignments required)
    
    -- <<DEFAULT SIGNAL ASSIGNMENTS HERE>> --
    
    if rst = '1' then  -- clear LED buffers on reset

    -- <<RESET SIGNAL ASSIGNMENTS HERE>> --

    else
      case cnt is  -- There are 4 stages in the RAM/LED cycle (ADDR, DATA, CLK, WAIT).
                   -- Fill in each stage with the correct signal assignments.
                   -- Remember that this is where the LED contents are buffered, so
                   -- you need to do the shifting from the right to the left somewhere
                   -- in this cycle as well.
                   
        -- ADDR: Set output as RAM address
        when 1 =>

        -- <<ADDR STAGE ASSIGNEMNTS HERE>> --
          
        -- DATA: Get RAM contents from Data lines
        when 2 =>  

        -- <<DATA STAGE ASSIGNMENMTS HERE>> --
		      
		    -- CLK: Clock the Address Counter
        when 3 =>  

        -- <<CLK STAGE ASSIGNMENTS HERE>> --
          
        -- WAIT: keep things constant for the rest of the cycle
        when others =>
        
        -- <<WAIT STAGE ASSIGNEMNTS HERE>> --
        
      end case;
    end if;
  end process;
  
end control_arch;