VHDL FAQ

You may also want to consult the Errors and Warnings lists.

Q: Are there any online VHDL tutorials?

A1: Green Mountain Computing has a tutorial, or (same, different format)

A2: Check out the language assistant in the HDL editor for help with syntax and component code templates (in Tools menu of HDL editor, or first button after the dropbox in the middle of the toolbar.)

Q: Why did "operation fail" when I tried to create my component?

A: Maybe not enough memory. Foundation uses lots of RAM, and also it has a memory leak, so after a while you may not have enough RAM to work properly. Check the messages on the main screen for "could not allocate memory" error messages (red) (they don't use a popup to tell you, it just kinda happens...)

Q: Is there a way to check the syntax of my VHDL without having to create a macro?

A: use "Synthesis -> Check Syntax". (Also, second button on toolbar after dropbox ).

Q: Why isn't my VHDL component listed in the component library in the schematic editor?

A: You need to synthesize the design - in their respective editors select Project -> Create Macro from the menu (also third button on toolbar after dropbox). They need to synthesize without errors - you need to get the message "Symbol 'my_symbol' successfully created" at the end of the process. After this, the symbol should appear at the top of the component library in the schematic editor.

Q: Why does my VHDL not synthesize?

make sure that for busses you assign the right number of bits
match if/end if's, begin/end process's etc...<>
make sure you don't use any reserved words as variable or signal names (most are red, but there are many that are not) eg: number, operator, in, out, begin, end...
type mismatch: internal signals and ports use <=, variables use :=, comparison is =
if using INTEGER or NATURAL type, use decimal numbers (eg 10), not hex or binary (eg "1010", X"A").
logic states (STD_LOGIC) are in single quotes: '1', '0'
logic states for busses (STD_LOGIC_VECTOR) are in double quotes: "11110000" or X"F0"
line is never reached: check for duplicated conditions

You may also want to check the Errors or Warnings list, or the Xilinx answers database (paste in your error).

Q: How can I copy my error message from the HDL editor?

A: Synthesis -> View Report will open a new text editor window where you can copy your error or warning messages.

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VHDL FAQ

Created by Paul Berube, 2001