Xilinx Foundation Finite State Machine FAQ

Q: How do I create a state machine?

A: I recommed that you start your state machine using the wizard. (right-click, look at the context menu and/or select "properties" for everything - this is how you can change a lot of stuff)

• create the I/O pins you need (you must have one input that you use as clk) 
• create any internal signals you need 
• set the state machine clk by r-clicking the background and selecting properties
• create your states. make sure not to give them reserved word state names (like begin, end, case, if...) 
• create transitions between your states 
• set the conditions on the transitions (as necessary)
• set state actions (what happens in this state - entry action, state action, and/or exit action) and/or transition actions (what happens when you use this transition)
• add a reset (synchronous or asynchronous, r-click)
• set the default and trap states (r-click the state, select the menu item)
• create the macro and test it out!

Q: How can I save an image of my state machine?

A1: Select everything in your design, and copy it.  Open paint, and make sure that the image size is quite large (like full screen), because when you paste in your state machine, it will fit in the image size (i.e. if you have a small image, then you'll get a really small state machine image that you can't read).  Paste in your state machine and save the .bmp file.

A2: Zoom your state machine to a large enough size (use the zoom-select tool, it's the magnifying glass on the tool bar).  Then, take a window capture with ALT+Printscreen.  Paste this into paint, and crop the image to be just the state machine.
 

Q: I changed my state machine, but the changes were not reflected in the generated HDL code.

A: Make sure to save - the VHDL won't change until you do so.
 

Q: How can I get my long state change conditions to go on more than one line?

A: R-click -> properties. Go to the editor tab. You can add press enter here to make it take as many lines as you like.
 

Q: The state machine says there are errors, an highlights a box in red - but there is nothing wrong in that box!!

A: Like the famous errors caused by missing semicolons in most languages, the same kind of error is occuring here. The error might be in the box, but it may also have happened in the generated code that is (hopefully) just before the code in that box. Unfortunately, the state machine diagram gives little indication of the order code generated, so take note of the line number, then generate HDL (from synthesis menu) and go take a look - try to find the error, and realize which piece of code (which box) it is really in. Note that the generate HLD is read-only, so you can't fix errors there, only in the state machine editor.
 

Q: Why isn't my <VHDL|FSM> listed in the library symbols in the schematic editor?

A: You need to "compile" both of these - in their respective editors select Project -> Create Macro from the menu. They need to compile without errors - you need to have gotten the message "Symbol 'mysymbol' successfully created" at the end of the process.
 

Q: Why do I get errors when I try to create a macro from the FSM (or VHDL)?

A: Remember:

• logic states are in single quotes: '1', '0'
• logic states for busses are in double quotes: "11110000" or X"F0"
• Did you miss a semicolon?
• Did you end every block (ifs, processes, architectures...)
• If syntax: if ___ then __; ... ; __ elsif __; ... ; else __; ... ; end if; Check it out in the Language Assistant for an example.
• Don't name states in the state machine reserved words... you can check by looking at the code - if a state name is red, that's BAD!!
• FSM conditions (red/pink, no box) don't end in a semicolon.
• FSM actions (black, in box) DO end in a semicolon.
• Did you make sure that I/O busses have the correct range?
• Finally, look at the generated code - you might just see something there that you can't/didn't see in the diagram

Q: Error: Enabling not allowed outside wait?

A: Try making the signal you are setting a registered signal instead of combinational.

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Created by Paul Berube, 2001